Analog switch circuit and signal attenuator employing an analog switch circuit

Claim 2

An analog switch circuit, comprising: an output terminal connected to a load having a given impedance, an input terminal connected to an input signal source having an impedance lower than the impedance of said load, a control signal input terminal receiving a control signal, first transfer gate means including a first P-type and a first N-type field-effect transistor, each having first, second, and third electrodes, each of said first electrodes being commonly connected to said output terminal, and each of said second electrodes being commonly connected to said input terminal, second transfer gate means including a second P-type and a second N-type field-effect transistor, each including first, second, and third electrodes, each of said second transfer gate means first electrodes being commonly connected and being connected in parallel with said commonly connected first electrodes of said first transfer gate means, each of said second electrodes of said second transfer gate means being commonly connected and being connected in parallel with said commonly connected second electrodes of said first transfer gate means, said second P-type and N-type field effect transistors each having a gate size smaller than that of said first P-type and N-type field effect transistors included in said first transfer gate means, and control means responsive to a control signal supplied to said control signal input terminal for applying a signal to each one of said third electrodes of said second transfer gate means so that said second transfer gate means is first turned on and for applying thereafter a signal to each one of said third electrodes of said first tranfer gate means so that said first gate means is then turned on.

Claim 3

An analog switch circuit in accordance with claim 1, which further comprises first and second constant current source means, each providing a constant current, and wherein said control means includes means responsive to said control signal for supplying constant current from said first and second constant current source means to the third electrodes of said first and second transfer gate means, respectively.

Claim 4

An analog switch circuit in accordance with claim 1, wherein said control means comprises means responsive to a control signal applied to said control signal input terminal for turning off said first transfer gate means with said second transfer gate means kept turned on.

Claim 5

An analog switch circuit in accordance with claim 3, wherein said control means comprises delay means for allowing said control signal applied to said control signal input terminal to be delayed for a predetermined time period, and means responsive to said control signal turning from a first logical state to a second logical state for turning on said second transfer gate means and responsive to said control signal turning from a second logical state to a first logical state for retaining said second transfer gate means in an on-state for said predetermined time period as a function of the output from said delay means.

Claim 6

A signal attenuator employing an analog switch circuit, comprising an output terminal connected to a load having a given impedance, an input terminal connected to an input signal source having an impedance lower than the impedance of said load, bias voltage generating means for generating a bias voltage, resistor voltage dividing means including a plurality of resistors connected in series between said input terminal and said bias voltage generating means, first transfer gate means provided corresponding to each said resistor and each gate means including a first P-type and a first N-type field-effect transistor, each having first, second, and third electrodes, all of said first electrodes of said first transfer gate means being commonly connected to said output terminal and, each of said second electrodes of respective first transfer gate means being commonly connected to an input end of its corresponding resistor, second transfer gate means including a second P-type and a second N-type field-effect transistor, each including first, second, and third electrodes, each of said first electrodes of said second transfer gate means being commonly connected to said output terminal, and each of said second electrodes of said second transfer gate means being commonly connected to said bias voltage generating means, third transfer gate means including a third P-type and a third N-type field-effect transistor, each including first, second, and third electrodes, each of said first electrodes of said third transfer gate means being commonly connected and being connected in parallel with said first electrodes of said second transfer gate means, each of said second electrodes of said third transfer gate means being commonly connected and being connected in parallel with said second electrodes of said second transfer gate means, said third P-type and third N-type field-effect transistors each having a gate size smaller than that of said second P-type and second N-type field-effect transistors included in said second transfer gate means, and control signal generating means for generating a plurality of control signals for turning on or off in succession each said first transfer gate means and said second transfer gate means, control means responsive to a control signal supplied to a control signal input terminal for applyiong a signal to said third electrodes of said second transfer gate means so that said second transfer gate means is first turned on and for applying thereafter signals to said first transfer gate means so that said first transfer gate means are then turned on.

Claim 7

A signal attenuator employing an analog switch circuit, comprising an output terminal connected to a load having a given impedance, an input terminal connected to an input signal source having an impedance lower than the impedance of said load, bias voltage generating means for generating a bias voltage, resistor voltage dividing means including a plurality of resistors connected in series between said input terminal and said bias voltage generating means, first transfer gate means provided corresponding to each said resistor and each gate means including a first P-type and a first N-type field-effect transistor, each having first, second, and third electrodes, all of said first electrodes of said first transfer gate means being commonly connected to said output terminal and, each of said second electrodes of respective first transfer gate means being commonly connected to an input end of its corresponding resistor, second transfer gate means including a second P-type and a second N-type field-effect transistor, each including first, second, and third electrodes, each of said first electrodes of said second transfer gate means being commonly connected to said output terminal, and each of said second electrodes of said second transfer gate means being commonly connected to said bias voltage generating means, third transfer gate means including a third P-type and a third N-type field-effect transistor, each including first, second, and third electrodes, each of said first electrodes of said third transfer gate means being commonly connected and being connected in parallel with said first electrodes of said second transfer gate means, each of said second electrodes of said third transfer gate means being commonly connected and being connected in parallel with said second electrodes of said second transfer gate means, said third P-type and third N-type field-effect transistors each having a gate size smaller than that of said second P-type and second N-type field-effect transistors included in said second transfer gate means, and control signal generating means for generating a plurality of control signals for turning on or off in succession each said first transfer gate means and said second transfer gate means, control means responsive to a control signal supplied to a control signal input terminal for applyiong a signal to said third electrodes of said second transfer gate means so that said second transfer gate means is first turned on and for applying thereafter signals to said first transfer gate means so that said first transfer gate means are then turned on.

Claim 8

A signal attenuator in accordance with claim 5, wherein said control means comprises means responsive to a control signal from said control signal generating means for turning off said second transfer gate means with said third transfer gate means kept turned on.

Claim 9

A signal attenuator in accordance with claim 5, which further comprises: first and second constant current source means each providing a constant current, and wherein said control means includes means responsive to said control signal for supplying constant current from said first and second constant current source means to the third electrodes of said first, second, and third transfer gate means, respectively.

Claim 10

A signal attenuator in accordance with claim 5, wherein said control signal generating means comprises a command key for commanding a switching operation of said first transfer gate means or said second transfer gate means, pulse signal generating means responsive to said command from said command key for generating a pulse signal, counting means for counting said pulse signal, and a decoder for decoding the output from said count means for providing the decoded output as said control signal.