US4618945A
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1983-07-26
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Granted: 1986-10-21
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Expires: 2003-07-26
Abstract
Abstract A semiconductor memory device has a plurality of memory cells arranged in a two-dimensional matrix array, word lines for connecting memory cells of each row to a row decoder, and bit lines for connecting memory cells of each column to a column decoder. The word lines include first word lines each of which is connected to several memory cells in each column section of one row. The word lines also include a second word line connected to the first word lines of each row through corresponding switches. In response to a column address signal, one of the switches of each row is turned on, so that one of the first word lines is connected to the corresponding second word line.
Inventors
- 👤 Takayasu Sakurai
- 👤 Tetsuya Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
114 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns, said memory cells in each of said rows being divided into a plurality of column sections; first word lines each connected to the memory cells in a different one of said column sections, said first word lines being organized into groups of word lines such that the memory cells connected to the first lines in each group of word lines are all in the same row of memory cells; second word lines; and switching means for connecting each of said second word lines to a different one of said group of first word lines.
Claim 2
Dependent Claim
114 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns, said memory cells in each of said rows being divided into a plurality of column sections; first word lines each connected to the memory cells in a different one of said column sections, said first word lines being organized into groups of word lines such that the memory cells connected to the first lines in each group of word lines are all in the same row of memory cells; second word lines; and switching means for connecting each of said second word lines to a different one of said group of first word lines.
Claim 3
Dependent Claim
60 words
A device according to claim 1, wherein said switching means comprises switches which are each connected between a different one of said second word lines and a different one of said first word lines in said corresponding group of first word lines, and which are controlled by a column section selection signal generated in response to a column address signal.
Claim 4
Dependent Claim
107 words
A device according to claim 2, wherein each said switch comprises a first MOSFET, a drain of which is connected to a different one of said second word lines and a source of which is connected to a different one of said first word lines in said corresponding group of first word lines, and a second MOSFET, a drain of which is connected to said different one of said first word lines in said corresponding group of first word lines and a source of which is connected to a reference power source, the column section selection signal being supplied to gates of said first and second MOSFETs.
Claim 5
Dependent Claim
23 words
A device according to claim 3, wherein said first and second MOSFETs are MOSFETs of different channel types whose gates are commonly connected.
Claim 6
Dependent Claim
43 words
A device according to claim 3, wherein said first and second MOSFETs are MOSFETs of the same channel type, a signal obtained by inverting a signal supplied to a gate of said first MOSFET being supplied to a gate of said second MOSFET.
Claim 7
Dependent Claim
77 words
A device according claim 2, wherein each said switch comprises a MOSFET, a drain of which is connected to a different one of said second word lines and a source of which is connected to a different one of said first word lines in said corresponding group of first word lines, and a resistor connected between said different one of said first word lines in said corresponding group of first word lines and a reference power source.
Claim 8
Dependent Claim
110 words
A device according to claim 2, wherein each said switch comprises a first MOSFET, a gate of which is connected to a different one of said second word lines and a source of which is connected to one of said first word lines in said corresponding group of first word lines, and a second MOSFET, a drain of which is connected to said different one of said first word lines in said corresponding group of first word lines and source of which is connected to a reference power source, the column section selection signal being supplied to a drain of said first MOSFET and a gate of said second MOSFET.
Claim 9
Dependent Claim
70 words
A device according to claim 2, wherein each said switch comprises a MOSFET, a gate of which is connected to a different one of said second word lines and a source of which is connected to a different one of said first word lines in said corresponding group and first word lines, and a resistor connected between said different one of said first word lines and a reference power source.
Claim 10
Dependent Claim
22 words
A device according to claim 2, wherein each said switch is connected at a center of one of said first word lines.
Claim 11
Dependent Claim
14 words
A device according to claim 2, wherein each said switch is a NOR gate.
Claim 12
Dependent Claim
36 words
A device according to claim 1, wherein each said first word line is formed of a first layer of polycrystalline silicon, and each said second word line is formed of a second layer of polycrystalline silicon.
Claim 13
Dependent Claim
38 words
A device according to claim 11, wherein each said memory cell is a static memory cell with a polycrystalline silicon high-resistance load, and each said second word line is formed by decreasing a resistance of said high-resistance load.
Claim 14
Dependent Claim
35 words
A device according to claim 1, wherein each said first word line is formed of a first layer of polycrystalline silicon, and each said second word line is formed of a second layer of aluminum.
Claim 15
Dependent Claim
107 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns, said memory cells of each column being divided into a plurality of row sections; first bit lines each connected to the memory cells in a different one of said row sections, said first bit lines being divided into groups of first bit lines such that the memory cells in each group of first bit lines are all in the same column; second bit lines; and switching means for connecting each of said second bit lines to a different corresponding one of said group of first bit lines.
Claim 16
Dependent Claim
107 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a two-dimensional matrix array of rows and columns, said memory cells of each column being divided into a plurality of row sections; first bit lines each connected to the memory cells in a different one of said row sections, said first bit lines being divided into groups of first bit lines such that the memory cells in each group of first bit lines are all in the same column; second bit lines; and switching means for connecting each of said second bit lines to a different corresponding one of said group of first bit lines.
Claim 17
Dependent Claim
59 words
A device according to claim 14, wherein said switching means comprises switches which are each connected between a different one of said second bit lines and a different one of said first bit lines in said corresponding group of bit lines, and are each controlled by a row section selection signal generated in response to a row address signal.
Claim 18
Dependent Claim
57 words
A device according to claim 15, wherein each said switch is a MOSFET which is connected between a different one of said first bit lines in one of said groups of first bit lines and the corresponding one of said second bit lines, the row section selection signal being supplied to a gate of each said MOSFET.
Claim 19
Dependent Claim
14 words
A device according to claim 15, wherein each said switch is a bidirectional amplifier.
Claim 20
Dependent Claim
34 words
A device according to claim 1, wherein each said first bit line is formed of a first layer of aluminum, and each said second bit line is formed of a second layer of aluminum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |