US4628405A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit precision capacitor
Assignee: National Semiconductor Corp
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Filing: 1985-08-19
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Granted: 1986-12-09
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Expires: 2005-08-19
Abstract
Abstract A refractory metal or a refractory metal silicide is applied to a monolithic IC where capacitors are desired and then covered with an amorphous silicon coating. The coating protects the capacitor metal or silicide during IC fabrication. The capacitor dielectric is created by oxidizing the protective coating, leaving the interface continuous and free of native oxides and trapping states. The result is a capacitor that has a very low voltage coefficient of capacitance.
Inventors
- 👤 John A. Lippert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:45
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
93 words
A capacitor suitable for fabrication on a monolithic silicon integrated circuit, said capacitor having a very low voltage coefficient of capacitance and comprising: a first plate composed of a material selected from the group consisting of refractory metals and refractory metal silicides; a dielectric layer located on said first plate, said dielectric layer being characterized as having a very low incidence of interface trapping states where it contacts the first plate; a second plate located on top of said dielectric layer; and means for making electrical connnections to said first and second plates.
Claim 2
Dependent Claim
93 words
A capacitor suitable for fabrication on a monolithic silicon integrated circuit, said capacitor having a very low voltage coefficient of capacitance and comprising: a first plate composed of a material selected from the group consisting of refractory metals and refractory metal silicides; a dielectric layer located on said first plate, said dielectric layer being characterized as having a very low incidence of interface trapping states where it contacts the first plate; a second plate located on top of said dielectric layer; and means for making electrical connnections to said first and second plates.
Claim 3
Dependent Claim
16 words
The capacitor of claim 1 wherein said second plate comprises the metallization of said integrated circuit.
Claim 4
Dependent Claim
73 words
In the process for fabricating a capacitor on a monolithic silicon integrated circuit, the steps: depositing a first conduction layer on said integrated circuit, said first conduction layer being composed of a material selected from the group consisting of refractory metals and refractory metal silicides; depositing a protective layer on said first conduction layer; forming a dielectric layer on said first conduction layer; and forming a conductive counter electrode on said dielectric layer.
Claim 5
Dependent Claim
73 words
In the process for fabricating a capacitor on a monolithic silicon integrated circuit, the steps: depositing a first conduction layer on said integrated circuit, said first conduction layer being composed of a material selected from the group consisting of refractory metals and refractory metal silicides; depositing a protective layer on said first conduction layer; forming a dielectric layer on said first conduction layer; and forming a conductive counter electrode on said dielectric layer.
Claim 6
Dependent Claim
14 words
The process of claim 3 wherein said protective layer is composed of amorphous silicon.
Claim 7
Dependent Claim
17 words
The process of claim 4 wherein said dielectric layer is formed by oxidizing said amorphous silicon layer.
Claim 8
Dependent Claim
62 words
The process of claim 4 wherein said first layer is a refractory metal and said amorphous silicon layer is made very thin, with respect to said first layer, and including the additional steps of depositing said dielectric layer on said protective layer and annealing the composite layers to cause said protective layer to be absorbed into said first layer as a silicide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |