Erasable, programmable read-only memory device

Claim 1

An erasable, programmable read-only memory device comprising a plurality of erasable, programmable read-only memory cells of channel injection type formed in a semiconductor substrate of one conductivity type in a matrix shape, a plurality of bit lines extending on one major surface of said substrate, and a plurality of address lines extending on said one major surface of said substrate, each of said cells including a first impurity region of the opposite conductivity type formed in said substrate, a second impurity region of the opposite conductivity type formed in said substrate and electrically connected to the corresponding bit line, a channel region positioned between said first and second impurity regions, a floating gate electrode formed on said channel region via a first gate insulating film, and a control gate electrode formed on the floating gate electrode via a second gate insulating film and electrically connected to the corresponding address line, said second impurity region being so constituted that the intensity of electric field near said channel region in a depletion layer formed between said second impurity region and said substrate is weaker than that in a depletion layer formed between said first impurity region and said substrate when an inversed voltage of a predetermined level against said substrate is applied to said first and second impurity region, respectively, said device further comprising a first means for applying voltages to said first and second impurity regions and said control gate electrode of a selected cell such that electric channel current flows in one direction between said first and second regions of said selected cell in writing operation, and a second means for applying voltage to said first and second impurity regions and said control gate electrode of a selected cell such that electric channel current may flow in the opposite direction between said first and second impurity regions in reading operation.