Process and system for transmitting a refresh signal to a semiconductor memory

Claim 1

A circuit arrangement for the transmission of a refresh signal to a semi-conductor memory which is connected to a central computer bus having a plurality of different aggregates attached thereto, each with a designated priority relative to the others, in which the refresh signal originates from a central processing unit (CPU) at a specific priority in comparison to other aggregates connected to the computer bus, to be delivered to a semi-conductor memory, in which the refresh signal is divided to at least two chronologically consecutive sub-intervals and the transmission of the refresh signal during the duration of the first sub-interval has a lower priority onto the computer bus and that, in the case of transmission of the refresh signal not being possible during the duration of the first sub-interval, the transmission of the refresh signal onto the computer bus is achieved at higher priority during the duration of the later sub-interval, characterized as: that the refresh signal (24) is divided into two sub-intervals (TRFR 1, TRFR2) by applying a clock cycle to an input of a divider circuit (2, 3, 4) an output of the divider circuit is applied to an input of a D-flip-flop (5) which outputs said two sub-intervals, and that during the duration of the first sub-interval (TRFR 1), a controller (13, 14, 17) generates the associated refresh signal RFR for the semi-conductor memory, said controller comprises a flip-flop (13) for receiving the two sub-intervals (TRFR 1 and TRFR2) and for generating an output to an input of a further flip-flop 14, an output of said flip-flop 14 is connected to one input (input 11) of a NAND-gate (17), the other inputs of said NAND-gate (17) are connected to receive status signals (ADR, BSY) to indicate the transmission readiness of an address line and the computer bus are connected; and that during the later sub-interval, the first sub-interval signal (TRFR 1) changes its logic status, the signal on said one input (input 11) of the NAND-gate (17) and on the output of said flip-flop (14) is connected to the input (input 13) of a further NAND-gate (16) on whose other input (input 12) the first sub-interval signal (TRFR 1) is placed; and that the signal (P10) generated on the output (output 11) of the further NAND-gate (16) is placed as a higher level priority signal via a priority controller (19) onto the computer bus, with a result that the lower priority aggregates are caused to release the address line and the computer bus (26).