Front end of an operational amplifier

Claim 2

In an amplifier circuit having an input stage and an output stage, said amplifier circuit comprising: a small signal amplification means in said input stage for providing an output current in response to a differential input voltage; a large signal amplification means in said input stage connected electrically in parallel with said small signal amplification means for providing additional slew current, wherein said large signal amplification means includes an input means connected to an active load means connected to a high gain current mirror means for providing control over when the additional slew current will be added to the output of said small signal amplification means such that slew current is provided only when said input differential voltage is at least a predetermined value; and summing means coupled between the outputs of said small signal amplification means and said large signal amplification means for providing a combined output current to said output stage for said amplifier circuit.

Claim 3

The amplifier circuit of claim 1, wherein said large signal amplification input means includes two differential transistor pairs, each having two inputs connected in Parallel to a corresponding like pair of inputs of said small signal amplification means and two outputs, whereby depending upon the polarity and magnitude of the input differential voltage, one of the differential transistor pairs will cause slew current to either be sunk or supplied at one of said outputs of said large signal amplification means.

Claim 4

The amplifier circuit of claim 2, wherein said active load means is connected between respective outputs of said differential transistor pairs and inputs to said current mirror means for biasing said current mirror means to a non-conductive state when the differential input voltage is within said predetermined value and biasing said current mirror means to a conductive state when said differential input is greater than said predetermined value, a respective output of said high gain current mirror means is connected to said summing means for conducting slew current to said summing means when said current mirror means is in a conducting state.

Claim 5

The amplifier circuit of claim 3, wherein said small signal amplification means includes at least one differential transistor pair having two inputs and an output for providing a small signal current output which corresponds directly with a differential voltage input.

Claim 6

The amplifier circuit of claim 4, wherein said small signal amplification means further includes an output coupling means coupled between said output of said differential transistor pair and the input to said summing means, said output coupling means including a pair of current mirror means for reflecting to said summing means the output signal of said differential pair to said summing means.

Claim 7

The amplifier circuit of claim 1, wherein said large signal amplification input means includes a differential transistor pair having two inputs and two outputs, said transistor inputs connected in parallel to a corresponding like pair of inputs of said small signal amplification means, and said outputs connected to said active load means.

Claim 8

The amplifier circuit claim 6, wherein said active load means being connected between the outputs of said differential transistor pairs and the inputs to said high gain current mirror means for biasing said current means to a non-conductive state when the differential input voltage is within a specified value and biasing said current mirror means to a conductive state when said differential input voltage is greater than said specified value.

Claim 9

In an amplifier circuit having an input and an output stage, said circuit comprising: a small signal amplification means in said input stage for providing an output current in response to a differential input voltage, wherein said small signal amplification means includes two differential pairs of transistors each having two inputs and an output; a large signal amplification means in said input stage connected electrically in parallel with said small signal amplification means, wherein said large signal amplification means includes two differential transistor pairs, each having two inputs connected in parallel to a corresponding like pair of inputs of said small signal amplification means, for providing additional slew current to said output stage when said differential input voltage is at least a predetermined value or when slew rate limiting occurs, and an active load means connected to each of said transistor pair and a high gain current mirror means connected to each of said active load means for providing control over when the additional slew current will be added to the output of the small signal amplification means; and summing means coupled between the outputs of said small signal amplification means and said large signal amplification means for providing a combined output current for said amplifier circuit.

Claim 10

In an amplifier circuit having an input and an output stage, said circuit comprising: a small signal amplification means in said input stage for providing an output current in response to a differential input voltage, wherein said small signal amplification means includes two differential pairs of transistors each having two inputs and an output; a large signal amplification means in said input stage connected electrically in parallel with said small signal amplification means, wherein said large signal amplification means includes two differential transistor pairs, each having two inputs connected in parallel to a corresponding like pair of inputs of said small signal amplification means, for providing additional slew current to said output stage when said differential input voltage is at least a predetermined value or when slew rate limiting occurs, and an active load means connected to each of said transistor pair and a high gain current mirror means connected to each of said active load means for providing control over when the additional slew current will be added to the output of the small signal amplification means; and summing means coupled between the outputs of said small signal amplification means and said large signal amplification means for providing a combined output current for said amplifier circuit.

Claim 11

The amplifier circuit of claim 8, wherein said small signal amplification means will either sink or supply current at the output of said small signal amplification means depending upon the polarity of the input differential voltage.

Claim 12

The amplifier circuit of claim 9, wherein each differential transistor pair of said small signal amplification means includes a pair of current mirrors connected between the respective outputs of said small signal amplification means and said summing means for providing a small signal current at the output of the small signal amplification means which directly corresponds to said differential voltage input.

Claim 13

An amplifier circuit having an input and an output stage, comprising: a small signal amplification means in said input stage for providing an output current as a function of a differential input voltage, up to a slew rate limit; a slew enhancement means in said input stage connected in parallel with said small signal amplification means, for providing additional slew output current when said slew rate limit occurs, wherein said slew enhancement means includes an active load means and high gain current mirror means for providing control over when the additional slew current will be provided to the output of said small signal amplification means; summing means coupled between the outputs of said small signal amplification means and said slew enhancement means for providing a current output to said output stage for said amplifier circuit.

Claim 14

An amplifier circuit having an input and an output stage, comprising: a small signal amplification means in said input stage for providing an output current as a function of a differential input voltage, up to a slew rate limit; a slew enhancement means in said input stage connected in parallel with said small signal amplification means, for providing additional slew output current when said slew rate limit occurs, wherein said slew enhancement means includes an active load means and high gain current mirror means for providing control over when the additional slew current will be provided to the output of said small signal amplification means; summing means coupled between the outputs of said small signal amplification means and said slew enhancement means for providing a current output to said output stage for said amplifier circuit.

Claim 15

The amplifier circuit of claim 11, wherein said small signal amplification means includes a differential amplifier consisting of at least one differential transistor pair having two inputs and one output, for providing a small signal current output which corresponds directly with the differential voltage input.

Claim 16

The amplifier circuit of claim 12, wherein said small signal amplification means further includes at least one current mirror means coupled between the output of said small signal means and the input of said summing means.

Claim 17

The amplifier circuit of claim 13, wherein said slew enhancement means further includes two differential transistor pairs, the inputs of each pair being connected in parallel with the inputs of said small signal amplification means.

Claim 18

The amplifier circuit of claim 14, wherein, said active load means is connected between the respective output of said transistor pairs and the input of said current mirror means, said current mirror output connected to the input of said summing means, whereby slew current may be combined with the output of said small signal amplification means to form a combined output signal.

Claim 19

The amplifier circuit of claim 15, wherein said active load means biases said current mirror means to a non-conducting state when said differential input voltage is within said slew rate limit and in a conducting state when said differential input voltage is above said slew rate limit.

Claim 20

An amplifier circuit having an input and an output stage, said circuit comprising: a small signal amplificaton means in said input stage for providing an output current as a function of a differential input voltage, up to a slew rate limit, wherein said small signal amplication means includes two different pairs of transistors having two inputs and an output; a slew enhancement means in said input stage connected in parallel with said small signal amplification means, wherein said slew enhancement means includes two differential transistor pairs for providing additional slew output current, and an active load means and a high gain current mirror means connected to said differential transistor pairs for biasing said slew enhancement means to provide said slew output current when said small signal amplification means reaches its slew rate limit; summing means coupled between the outputs of said small signal amplification means and said slew enhancement means for providing a current output to said output stage for said amplifier circuit.

Claim 21

An amplifier circuit having an input and an output stage, said circuit comprising: a small signal amplificaton means in said input stage for providing an output current as a function of a differential input voltage, up to a slew rate limit, wherein said small signal amplication means includes two different pairs of transistors having two inputs and an output; a slew enhancement means in said input stage connected in parallel with said small signal amplification means, wherein said slew enhancement means includes two differential transistor pairs for providing additional slew output current, and an active load means and a high gain current mirror means connected to said differential transistor pairs for biasing said slew enhancement means to provide said slew output current when said small signal amplification means reaches its slew rate limit; summing means coupled between the outputs of said small signal amplification means and said slew enhancement means for providing a current output to said output stage for said amplifier circuit.

Claim 22

The amplifier circuit of claim 17, wherein said small signal amplification means further includes a pair of current mirror means coupled between said small signal means and the input of said summing means.

Claim 23

The amplifier circuit of claim 18, wherein the inputs of each transistor pair of said slew enhancement means is connected in parallel with the inputs of each transistor pair of said small signal amplification means.