US4641284A
Expired / Lapsed
US
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Signal transmission circuit for a storage device
Assignee: Fujitsu Ltd
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Filing: 1985-01-29
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Granted: 1987-02-03
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Expires: 2005-01-29
Abstract
Abstract A circuit, having a plurality of input terminals connected to a common output terminal, for transmitting a signal with high fidelity and a small time delay. Each input terminal has a transfer MOS transistor, which isolates it from other terminals in a non-active state, and the input terminal is connected to the common output terminal when an input signal is applied to the input terminal. A buffer circuit, connected between the input terminal and the gate of the MOS transistor, is driven by the input signal and provides a driving signal to the gate electrode of the MOS transistor. The level of the driving signal is sufficiently high to make the MOS transistor conductive so as to transmit the input signal with substantially the same signal profile and an extremely small time lag.
Inventors
- 👤 Yasuo Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/14; G11C11/56; G11C11/5692; G11C8/00; G11C8/08; G11C8/10; G11C8/12; G11C8/18; G11C16/00; G11C16/02; G11C16/06; G11C16/08
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
115 words
A signal transmission circuit comprising: a common output terminal; and a plurality of input circuits connected to said common output terminal, each said input circuit comprising, an input terminal; a buffer circuit; and a metal insulator semiconductor (MIS) transistor, wherein the source-drain regions of said MIS transistor are connected to said input terminal and said output terminal, said buffer circuit being connected between said input terminal and the gate electrode of said MIS transistor, wherein said buffer circuit is driven by an input signal selectively applied thereto, wherein said MIS transistor is driven by said buffer circuit to a conductive state whereby said input signal is transmitted from said input terminal to said output terminal.
Claim 2
Dependent Claim
115 words
A signal transmission circuit comprising: a common output terminal; and a plurality of input circuits connected to said common output terminal, each said input circuit comprising, an input terminal; a buffer circuit; and a metal insulator semiconductor (MIS) transistor, wherein the source-drain regions of said MIS transistor are connected to said input terminal and said output terminal, said buffer circuit being connected between said input terminal and the gate electrode of said MIS transistor, wherein said buffer circuit is driven by an input signal selectively applied thereto, wherein said MIS transistor is driven by said buffer circuit to a conductive state whereby said input signal is transmitted from said input terminal to said output terminal.
Claim 3
Dependent Claim
28 words
A signal transmission circuit as set forth in claim 1, wherein said MIS transistor is a p-type, channel type transistor and said buffer circuit comprises a CMOS inverter.
Claim 4
Dependent Claim
28 words
A signal transmission circuit by claim 1, wherein said MIS transistor is an n-type, channel type transistor and said buffer circuit comprises two CMOS inverters connected in series.
Claim 5
Dependent Claim
278 words
A storage device comprising: a storage cell array means forming a matrix comprising a plurality of rows of storage cells for storing information; a reference storage cell array means comprising a plurality of rows of reference storage cells for providing reference signals, each row of reference storage cells providing one of a predetermined number of reference signals; a row of dummy storage cell means for simulating each transmission of a word line signal applied to a row of said storage cells and a row of said reference storage cells, and means for outputting a clock signal in response to said simulated word line signal; and a signal transmission circuit for transmitting said word line signal, simultaneously, to a selected row of said storage cells, to all rows of said reference storage cells, and to said row of dummy storage cell means, said signal transmission circuit comprising a common output terminal and a plurality of input circuits connected to said common output terminal, each said input circuit comprising an input terminal, a buffer circuit and a metal insulator semi-conductor (MIS) transistor, wherein the source-drain regions of said MIS transistor are connected to said input terminal and said output terminal, and wherein said buffer circuit is inserted between said input terminal and the gate electrode of said MIS transistor, each said buffer circuit being driven by a respective one of a plurality of word line signals applied as an input signal to said input terminal, said MIS transistor being driven into conduction by said buffer circuit receiving an input signal whereby said input signal is selectively transmitted from said input terminal to said output terminal as said word line signal.
Claim 6
Dependent Claim
278 words
A storage device comprising: a storage cell array means forming a matrix comprising a plurality of rows of storage cells for storing information; a reference storage cell array means comprising a plurality of rows of reference storage cells for providing reference signals, each row of reference storage cells providing one of a predetermined number of reference signals; a row of dummy storage cell means for simulating each transmission of a word line signal applied to a row of said storage cells and a row of said reference storage cells, and means for outputting a clock signal in response to said simulated word line signal; and a signal transmission circuit for transmitting said word line signal, simultaneously, to a selected row of said storage cells, to all rows of said reference storage cells, and to said row of dummy storage cell means, said signal transmission circuit comprising a common output terminal and a plurality of input circuits connected to said common output terminal, each said input circuit comprising an input terminal, a buffer circuit and a metal insulator semi-conductor (MIS) transistor, wherein the source-drain regions of said MIS transistor are connected to said input terminal and said output terminal, and wherein said buffer circuit is inserted between said input terminal and the gate electrode of said MIS transistor, each said buffer circuit being driven by a respective one of a plurality of word line signals applied as an input signal to said input terminal, said MIS transistor being driven into conduction by said buffer circuit receiving an input signal whereby said input signal is selectively transmitted from said input terminal to said output terminal as said word line signal.
References Cited (Backward Citations)
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |