Circuit arrangement for testing a digital circuit

Claim 1

Circuit arrangement for dynamic real time testing of a synchronous digital circuit having a clock pulse input, a stimulus input and a circuit node, wherein a digital test signal is produced at the circuit node of the digital circuit after a time delay, caused by the digital circuit, of τ seconds relative to the time of receipt of a signal at the stimulus input of the digital circuit, said arrangement comprising: clock pulse generator means for generating clock pulses; transmitter means connected to said clock pulse generator means and including a counter for counting the clock pulses and a digital signal generator means for generating a reproducible digital stimulus signal having a length corresponding to a predetermined count of said counter, said transmitter means having a clock pulse output and being connected for coupling a number of clock pulses corresponding to the predetermined count of said counter to the clock pulse input of the digital circuit and for delivering the digital stimulus signal to the stimulus input of the digital circuit in synchronism with the clock pulses coupled to the clock pulse input; delay means having an input and an output, the input of said delay means being connected to the clock pulse output of said transmitter for delaying the clock pulses by a time delay corresponding to the τ second time delay of the digital test signal caused by the digital circuit; and analyzing means having a first input arranged for receiving the digital test signal from the digital circuit and a second input connected to the output of said delay means for receiving the same number of clock pulses, delayed by τ seconds, coupled to the digital circuit, said analyzing means including feedback shift register means for compressing the test signal into a test signature which can be checked for errors by comparison with a desired signature.