US4642566A
Expired / Lapsed
US
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Method for the registration and representation of signals in the interior of integrated circuits by considering edge steepness and apparatus for implementing the method
Assignee: Siemens AG
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Filing: 1984-07-19
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Granted: 1987-02-10
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Expires: 2004-07-19
Abstract
Abstract A respective threshold circuit is provided for defining upper and lower thresholds representing logic levels of signals occuring within integrated circuits. The chronological position of a signal edge and the steepness of the signal edge are defined with the assistance of the two thresholds.
Inventors
- 👤 Peter Fazekas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
179 words
A method for registering signals at integrated circuits, the signals having logic levels, comprising the steps of: defining upper and lower thresholds for the logic levels 1 and 0, respectively, and setting respective thresholds at respective input circuits for the logic level; positioning a pulsed primary beam to a measuring location of the integrated circuit to generate secondary particles; detecting the secondary particles and generating a corresponding signal to be registered; applying the signal to be registered to the two input circuits to detect and provide position signals indicating the chronological positions of signal edges at the logic levels by comparing the signal to the thresholds and producing a logical 1 at times in which the signal is greater than the upper threshold and the logical 0 at times when the signal is smaller than the lower threshold, and determining the signal edges from the chronological spacing of successive signal regions having logical levels 0 and 1, whereby the chronological position of the signal edges is defined by the times at which the signal is equal to the thresholds.
Claim 2
Independent Claim
179 words
A method for registering signals at integrated circuits, the signals having logic levels, comprising the steps of: defining upper and lower thresholds for the logic levels 1 and 0, respectively, and setting respective thresholds at respective input circuits for the logic level; positioning a pulsed primary beam to a measuring location of the integrated circuit to generate secondary particles; detecting the secondary particles and generating a corresponding signal to be registered; applying the signal to be registered to the two input circuits to detect and provide position signals indicating the chronological positions of signal edges at the logic levels by comparing the signal to the thresholds and producing a logical 1 at times in which the signal is greater than the upper threshold and the logical 0 at times when the signal is smaller than the lower threshold, and determining the signal edges from the chronological spacing of successive signal regions having logical levels 0 and 1, whereby the chronological position of the signal edges is defined by the times at which the signal is equal to the thresholds.
Claim 3
Dependent Claim
46 words
The method of claim 1, and further defined by the steps of: sampling the input signals at a first rate to determine the edge positions; and sampling the input signals at a second, higher rate in the areas of the edges to determine the edge steepness.
Claim 4
Dependent Claim
19 words
The method of claim 2, and further comprising the step of: storing the measured result in a highly-compressed form.
Claim 5
Dependent Claim
292 words
Apparatus for registering signals S at integrated circuits, the signals having two logic levels, comprising: a pulsed primary beam and means for positioning the beam to a measuring location of an integrated circuit to trigger the emission of secondary particles; detection means for detecting the secondary particles and producing a corresponding signal S; first and second comparators each including first and second inputs and an output, said first inputs connected to said detection means and serving for receiving the signals S to be registered; first and second adjustable reference means connected to respective ones of said second inputs for setting respective first and second thresholds U1, U0 for said comparators; and logic means connected to said outputs of said comparators, said logic means including first, second and third outputs and operable to provide a first output signal at said first output when said input signal S is greater than the first threshold U1, a second output signal at said second output when said input signal S is between the first threshold U1 and the second threshold U0, and a third output signal when said input signal S is less than said second threshold U0, said logic means including first, second and third AND gates, said first AND gate including a first input connected to said output of said first comparator and a second input connected to said output of said second comparator, said second AND gate including an inverting first input connected to said output of said first comparator and a second input connected to said output of said second comparator and said third AND gate including an inverting first input connected to said output of said first comparator and an inverting second input connected to said output of said second comparator.
Claim 6
Dependent Claim
292 words
Apparatus for registering signals S at integrated circuits, the signals having two logic levels, comprising: a pulsed primary beam and means for positioning the beam to a measuring location of an integrated circuit to trigger the emission of secondary particles; detection means for detecting the secondary particles and producing a corresponding signal S; first and second comparators each including first and second inputs and an output, said first inputs connected to said detection means and serving for receiving the signals S to be registered; first and second adjustable reference means connected to respective ones of said second inputs for setting respective first and second thresholds U1, U0 for said comparators; and logic means connected to said outputs of said comparators, said logic means including first, second and third outputs and operable to provide a first output signal at said first output when said input signal S is greater than the first threshold U1, a second output signal at said second output when said input signal S is between the first threshold U1 and the second threshold U0, and a third output signal when said input signal S is less than said second threshold U0, said logic means including first, second and third AND gates, said first AND gate including a first input connected to said output of said first comparator and a second input connected to said output of said second comparator, said second AND gate including an inverting first input connected to said output of said first comparator and a second input connected to said output of said second comparator and said third AND gate including an inverting first input connected to said output of said first comparator and an inverting second input connected to said output of said second comparator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-09 | 1990-08-11 | 1991-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-09 | 1994-08-11 | 1995-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-09 | 1998-08-11 | 1999-02-10 | $7700.00 | Window Closed / Lapsed |