US4652994A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for transmitting data to auxiliary memory device
Assignee: Fanuc Corp
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Filing: 1985-01-23
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Granted: 1987-03-24
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Expires: 2005-01-23
Abstract
Abstract A system for exchanging data between a microprocessor (1) and an auxiliary memory device (10) connected to the microprocessor (1). A plurality of data exchange common RAMs (24, 25) are arranged in the auxiliary memory device (10), and the operating states of the common RAMs (24, 25) are stored in memory means (26, 27), respectively. Data exchange is performed through a common RAM (24, 25) which is not being used in accordance with the storage content of said memory means (26, 27), thereby decreasing the waiting time for data transmission/reception.
Inventors
- 👤 Seiichi Hattori
- 👤 Kunio Kanda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:36
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A system for transmitting data to or receiving data from an auxiliary memory device, comprising: a microprocessor; an auxiliary memory device connected to said microprocessor, said auxiliary memory device including: a plurality of data transmitting/receiving common random access memories connected to said microprocessor; and memory means, connected to said microprocessor, for storing an operating state of each of said plurality of data transmitting/receiving common random access memories, so that upon detection of writing of a command from said microprocessor in a given one of said plurality of common random access memories, one of said memory means which corresponds to said given common random access memory, is set, after processing of the command is completed, said one memory is reset, and said microprocessor supplies another command to one of said plurality of common random access memories which corresponds to memory means which is not set upon searching of said memory means.
Claim 2
Independent Claim
150 words
A system for transmitting data to or receiving data from an auxiliary memory device, comprising: a microprocessor; an auxiliary memory device connected to said microprocessor, said auxiliary memory device including: a plurality of data transmitting/receiving common random access memories connected to said microprocessor; and memory means, connected to said microprocessor, for storing an operating state of each of said plurality of data transmitting/receiving common random access memories, so that upon detection of writing of a command from said microprocessor in a given one of said plurality of common random access memories, one of said memory means which corresponds to said given common random access memory, is set, after processing of the command is completed, said one memory is reset, and said microprocessor supplies another command to one of said plurality of common random access memories which corresponds to memory means which is not set upon searching of said memory means.
Claim 3
Dependent Claim
77 words
A system according to claim 1, wherein one of said microprocessor and said auxiliary memory device is a high-speed operation unit, and wherein said auxiliary memory device further comprises a priority order control circuit, connected to said microprocessor, for selecting the one of said auxiliary memory device and said microprocessor which is the high-speed operation unit, when said auxiliary memory device and said microprocessor simultaneously access an identical one of said plurality of common random access memories.
Claim 4
Independent Claim
192 words
A system for transmitting and receiving data, comprising: a microprocessor for generating read and write commands; and an auxiliary memory device, connected to said microprocessor, for receiving the read and write commands from said microprocessor, said auxiliary memory device including: at least two data transmitting/receiving common random access memories coupled to said microprocessor; and at least two memory means respectively corresponding to said at least two transmitting/receiving common random access memories and coupled to said microprocessor, for storing an operating state of the corresponding one of said at least two data transmitting/receiving common random access memories; and control means for setting the corresponding one of said at least two memory means when said microprocessor provides a read or write command to a selected one of said at least two data transmitting/receiving common random access memories, for resetting said one of said at least two memory means after processing of the read or write command is completed, said microprocessor supplying another read or write command to one of said at least two data transmitting/receiving common random access memories which corresponds to one of said at least two memory means which is not set.
Claim 5
Independent Claim
192 words
A system for transmitting and receiving data, comprising: a microprocessor for generating read and write commands; and an auxiliary memory device, connected to said microprocessor, for receiving the read and write commands from said microprocessor, said auxiliary memory device including: at least two data transmitting/receiving common random access memories coupled to said microprocessor; and at least two memory means respectively corresponding to said at least two transmitting/receiving common random access memories and coupled to said microprocessor, for storing an operating state of the corresponding one of said at least two data transmitting/receiving common random access memories; and control means for setting the corresponding one of said at least two memory means when said microprocessor provides a read or write command to a selected one of said at least two data transmitting/receiving common random access memories, for resetting said one of said at least two memory means after processing of the read or write command is completed, said microprocessor supplying another read or write command to one of said at least two data transmitting/receiving common random access memories which corresponds to one of said at least two memory means which is not set.
Claim 6
Dependent Claim
93 words
A system according to claim 3, wherein one of said microprocessor and said auxiliary memory device is a high-speed operation unit, further comprising at least two priority order control circuits, connected to said control means and said microprocessor, and corresponding to said at least two data transmitting/receiving common random access memories, for selecting the one of said auxiliary memory device and said microprocessor which is the high-speed operation unit, when said auxiliary memory device and said microprocessor simultaneously access the same one of said at least two data transmitting/receiving common random access memories.
Claim 7
Dependent Claim
21 words
A system according to claim 4, wherein said auxiliary memory device includes an external memory medium coupled to said control means.
Claim 8
Dependent Claim
15 words
A system according to claim 5, wherein said external memory medium comprises a magnetic disk.
References Cited (Backward Citations)
US4532587A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |