US4653177A
Expired / Lapsed
US
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Method of making and selectively doping isolation trenches utilized in CMOS devices
Assignee: Nokia Bell Labs
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Filing: 1985-07-25
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Granted: 1987-03-31
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Expires: 2005-07-25
Abstract
Abstract It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.
Inventors
- 👤 Joseph Lebowitz
- 👤 Thomas E. Seidel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:08
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6324; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P76/00; H10P76/40; H10P76/405; H10P76/408; H10P76/4085; H10W10/01; H10W10/011; H10W10/014; H10W10/0148
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
68 words
A method of independently doping n- and p-type regions of isolation trenches formed in a CMOS device, said method comprising the steps of nonlithographically forming a dopant mask only on the p-type region of each trench, doping only the n-type region of each trench with an n-type dopant, removing said dopant mask, and then simultaneously doping both n- and p-type regions of each trench with a p-type dopant.
Claim 2
Independent Claim
68 words
A method of independently doping n- and p-type regions of isolation trenches formed in a CMOS device, said method comprising the steps of nonlithographically forming a dopant mask only on the p-type region of each trench, doping only the n-type region of each trench with an n-type dopant, removing said dopant mask, and then simultaneously doping both n- and p-type regions of each trench with a p-type dopant.
Claim 3
Dependent Claim
13 words
A method as in claim 1 wherein said forming step includes selective anodization.
Claim 4
Dependent Claim
23 words
A method as in claim 2 wherein the p-type region of each trench is etched and rendered porous in a wet anodization step.
Claim 5
Dependent Claim
23 words
A method as in claim 3 wherein the p-type region of each trench is then oxidized to form a mask comprising silicon dioxide.
Claim 6
Dependent Claim
33 words
A method as in claim 2 wherein the p-type region of each trench is selectively converted to a mask comprising silicon dioxide in a one-step dry anodization procedure carried out in a plasma.
Claim 7
Independent Claim
90 words
A method of fabricating a CMOS device of the type that includes isolation trenches between adjacent p- and n-type regions of said device, said method comprising the steps of nonlithographically forming a dopant mask only on one region of each trench, doping only the other region of each trench with a dopant of the same conductivity type as that of said other region, removing said dopant mask, and then simultaneously doping both regions of each trench with a dopant of the same conductivity type as that of said one region.
Claim 8
Independent Claim
90 words
A method of fabricating a CMOS device of the type that includes isolation trenches between adjacent p- and n-type regions of said device, said method comprising the steps of nonlithographically forming a dopant mask only on one region of each trench, doping only the other region of each trench with a dopant of the same conductivity type as that of said other region, removing said dopant mask, and then simultaneously doping both regions of each trench with a dopant of the same conductivity type as that of said one region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |