Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs

Claim 1

A cache memory control system suitable for a data processing device including a main memory unit for storing programs divided into segments which correspond to a logical unit of storage and a central processing unit coupled to the main memory unit via a memory bus, said cache memory control system comprising: first and second cache memory units each being comprised of any of full-associative, set-associative, or direct-map cache memory units, and each storing a part of the contents of said main memory unit in such a way that one of said first and second cache memory units stores a system program or user program with higher priority and the other cache memory unit stores a system program with lower priority; segment descriptor means including a base field for specifying the start address of a corresponding program segment in said main memory, a size field for specifying the size of the segment, a read/write field for specifying a read operation or write operation, an enable/disable field for specifying the enable or disable of the access to said cache memory units, and a cache memory unit selection field for selecting one of said first and second cache memory units depending on the access of the system or user program with higher or lower priority; cache memory unit address generating means for generating a cache address for one of said cache memory units based on the contents of said base field of said segment descriptor means and an address in a segment, which corresponds to the program to be accessed and is supplied from said central processing unit; and means for supplying the contents of said cache memory unit selection field of said segment descriptor means to said first cache memory unit and supplying the inverted contents of said cache memory unit selection field to said second cache memory unit, thereby selecting one of said first and second cache memory units.