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US4656605A Expired / Lapsed US ⏱️ 0.0 years remaining

Single in-line memory module

Assignee: Wang Laboratories Inc
•
Filing: 1986-06-12
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Granted: 1987-04-07
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Expires: 2006-06-12
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Abstract

Abstract What is disclosed is a memory module to and from which multibit binary words are stored and read out. Each multibit binary word comprises a standard word size and another memory bit that may be used for purposes such as parity checking. The modules may be mounted on a printed circuit mother board from which power, control signals and binary words are applied to and taken from the module.

Inventors

  • 👤 James E. Clayton

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 08:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032; G11; G11C; G11C5/00; G11C5/06; G11C5/066; H; H10; H10W; H10W90/00; H10W90/20

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 301 words
A memory module for installation on a printed circuit motherboard comprising: eight data memory chips for storing digital data, each having a data input and output, a control input, and an address input, and each being packaged in a plastic leaded chip carrier; a ninth memory chip for storing error detection and correction information associated with the eight data memory chips, said ninth memory chip having a data input and output, a control input and an address input interconnected with those of the eight memory chips, and a control input to provide writing in or reading out of the ninth memory chip at times other than when said bytes of digital information are written into or read out of the eight data memory chips to thereby facilitate said error detection and correction operation; an epoxy-glass printed circuit board substrate having a length and width adequate for mounting thereon only in a single row said nine memory chips and for interconnecting the control inputs and the address inputs of the memory chips so that bytes of digital information may be input to or output from the memory chips one at a time; the substrate including thirty terminals for providing access to the data inputs and outputs, control inputs, and address inputs of the nine memory chips to enable reading and writing of bytes of digital information into and out of the eight memory chips and to enable reading and writing of error detection and correction information into and out of the eight memory chips; support means for supporting the memory module at an angle with respect to the printed circuit motherboard when the memory module is installed thereon; and eight decoupling capacitors, mounted on said substrate and connected between the nine memory chips, for supressing transient voltage spikes between said memory chips.
Claim 2
Dependent Claim 301 words
A memory module for installation on a printed circuit motherboard comprising: eight data memory chips for storing digital data, each having a data input and output, a control input, and an address input, and each being packaged in a plastic leaded chip carrier; a ninth memory chip for storing error detection and correction information associated with the eight data memory chips, said ninth memory chip having a data input and output, a control input and an address input interconnected with those of the eight memory chips, and a control input to provide writing in or reading out of the ninth memory chip at times other than when said bytes of digital information are written into or read out of the eight data memory chips to thereby facilitate said error detection and correction operation; an epoxy-glass printed circuit board substrate having a length and width adequate for mounting thereon only in a single row said nine memory chips and for interconnecting the control inputs and the address inputs of the memory chips so that bytes of digital information may be input to or output from the memory chips one at a time; the substrate including thirty terminals for providing access to the data inputs and outputs, control inputs, and address inputs of the nine memory chips to enable reading and writing of bytes of digital information into and out of the eight memory chips and to enable reading and writing of error detection and correction information into and out of the eight memory chips; support means for supporting the memory module at an angle with respect to the printed circuit motherboard when the memory module is installed thereon; and eight decoupling capacitors, mounted on said substrate and connected between the nine memory chips, for supressing transient voltage spikes between said memory chips.

References Cited (Backward Citations)

US3599146A Cited
GB1439333A Cited
US3972033A Cited
GB1557684A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-04-06 1990-10-06 1991-04-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-04-06 1994-10-06 1995-04-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-04-06 1998-10-06 1999-04-07 $7700.00 Window Closed / Lapsed

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