Patent US1344007A successfully refreshed from Google Patents.
US4656607A
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Electrically erasable programmable RAM
Assignee: Hitachi Ltd
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Filing: 1984-07-19
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Granted: 1987-04-07
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Expires: 2004-07-19
Abstract
Abstract In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.
Inventors
- 👤 Takaaki Hagiwara
- 👤 Toru Kaga
- 👤 Hiroo Masuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C16/00; G11C16/02; G11C16/04; G11C16/0408
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
399 words
A semiconductor memory including a plurality of memory cells arranged in a matrix with each of said memory cells being coupled to one of a plurality of first word lines for said memory, one of a plurality of second word lines of said memory and one of a plurality of bit lines for said memory, and further including a semiconductor substrate having a first conductivity type and at least first and second surface regions that are disposed in adjacent portions of said substrate, wherein said first and second surface regions are separated from one another by an oxide film for isolation, wherein each of said first and second surface regions has a memory cell formed therein, and wherein each of said memory cells comprises: an insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in a semiconductor layer over said substrate, a first insulating film formed on a surface region of said semiconductor layer which is disposed between source and drain regions, and a gate electrode formed on said first insulating film connected to said first line; and a memory element formed on said semiconductor substrate adjacent to said insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in said substrate, wherein one of said source or drain regions of said memory element is connected to said bit line, and the other of said drain or source regions of said memory element is connected to a predetermined potential, a second insulating film formed on said semiconductor substrate which extends over a surface region of said substrate between said source and drain regions of said memory element, wherein said semiconductor layer extends over said second insulating film to form a first electrode serving as a floating gate of said memory element connected to one of said drain or source regions of said insulated-gate field effect transistor, a third insulating film formed on said first electrode, and a second electrode serving as a control gate of said memory element formed on said third insulating film connected to said second word line, wherein a portion of said memory element is stacked on a portion of said insulated-gate field effect transistor, and further wherein at least a portion of said insulated-gate field effect transistor is formed on a fourth insulating film which is formed by the same process as said second insulating film.
Claim 2
Dependent Claim
399 words
A semiconductor memory including a plurality of memory cells arranged in a matrix with each of said memory cells being coupled to one of a plurality of first word lines for said memory, one of a plurality of second word lines of said memory and one of a plurality of bit lines for said memory, and further including a semiconductor substrate having a first conductivity type and at least first and second surface regions that are disposed in adjacent portions of said substrate, wherein said first and second surface regions are separated from one another by an oxide film for isolation, wherein each of said first and second surface regions has a memory cell formed therein, and wherein each of said memory cells comprises: an insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in a semiconductor layer over said substrate, a first insulating film formed on a surface region of said semiconductor layer which is disposed between source and drain regions, and a gate electrode formed on said first insulating film connected to said first line; and a memory element formed on said semiconductor substrate adjacent to said insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in said substrate, wherein one of said source or drain regions of said memory element is connected to said bit line, and the other of said drain or source regions of said memory element is connected to a predetermined potential, a second insulating film formed on said semiconductor substrate which extends over a surface region of said substrate between said source and drain regions of said memory element, wherein said semiconductor layer extends over said second insulating film to form a first electrode serving as a floating gate of said memory element connected to one of said drain or source regions of said insulated-gate field effect transistor, a third insulating film formed on said first electrode, and a second electrode serving as a control gate of said memory element formed on said third insulating film connected to said second word line, wherein a portion of said memory element is stacked on a portion of said insulated-gate field effect transistor, and further wherein at least a portion of said insulated-gate field effect transistor is formed on a fourth insulating film which is formed by the same process as said second insulating film.
Claim 3
Dependent Claim
31 words
The semiconductor memory as defined in claim 1, wherein said first electrode and one of said drain or source regions of said insulated-gate field effect transistor are the same semiconductor region.
Claim 4
Dependent Claim
22 words
The semiconductor memory as defined in claim 1, wherein said predetermined potential is either a ground potential or a power source potential.
Claim 5
Dependent Claim
29 words
The semiconductor memory as defined in claim 1, wherein the other of said drain or source regions of said insulated-gate field effect transistor is connected to said bit line.
Claim 6
Dependent Claim
27 words
The semiconductor memory as defined in claim 4, wherein said second electrode of said memory element is connected to the gate of said insulated-gate field effect transistor.
Claim 7
Dependent Claim
48 words
The semiconductor memory as defined in claim 1, which includes means for turning on said insulated-gate field effect transistor in a mode for writing data into said memory element, and for turning off said insulated-gate field effect transistor in a mode for reading data from said memory element.
Claim 8
Dependent Claim
47 words
The semiconductor memory as defined in claim 1, which includes means for applying a predetermined voltage to the second electrode of said memory element in a mode for reading data from said memory element, and means for identifying whether said memory element is turned on or off.
Claim 9
Dependent Claim
45 words
The semiconductor memory as defined in claim 1, which includes means for storing or discharging charge to the first electrode of said memory element through said insulated-gate field effect transistor which has been turned on, in a mode for writing data into said memory element.
Claim 10
Dependent Claim
20 words
The semiconductor memory as defined in claim 1, wherein said insulated-gate field effect transistor is an MOS (Metal-Oxide Semiconductor) transistor.
Claim 11
Dependent Claim
56 words
The semiconductor memory as defined in claim 1, wherein said surface region of said insulated-gate field effect transistor is formed to extend in a vertical direction perpendicular to said source and drain regions of said insulated-gate field effect transistor, and further wherein said channel region extends on a vertical side surface of said fourth insulating field.
Claim 12
Dependent Claim
375 words
A semiconductor memory including a plurality of memory cells arranged in a matrix with each of said memory cells being coupled to one of a plurality of first word lines for said memory, one of a plurality of second word lines for said memory and one of a plurality of bit lines for said memory, and further including a semiconductor substrate having a first conductivity type and at least first and second surface regions that are disposed in adjacent portions of said substrate, wherein said first and second surface regions are separated from one another by an oxide film for isolation, wherein each of said first and second surface regions has a memory cell formed therein, and wherein each of said memory cells comprises: an insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in a semiconductor layer over said substrate, a first insulating film formed on a surface region of said semiconductor layer which is disposed between source and drain regions, and a gate electrode formed on said first insulating film connected to said first line; and a memory element formed on said semiconductor substrate adjacent to said insulated-gage field effect transistor having a source and drain region formed by semiconductor regions in said substrate, wherein one of said source or drain regions of said memory element is connected to said bit lines, and the other of said drain or source regions of said memory element is connected to a predetermined potential, a second insulating film formed on a surface region of said semiconductor substrate between said source and drain regions of said memory element, wherein said semiconductor layer extends over said second insulating film to form a first electrode serving as a floating gate of said memory element connected to one of said drain or source regions of said insulated-gate field effect transistor, a third insulating film formed on said first electrode, and a second electrode serving as a control gate of said memory element formed on said third insulating film connected to said second word line, wherein said insulated-gate field effect transistor is formed so that said source and drain thereof and a channel region extending between said source and drain are formed on said oxide film.
Claim 13
Dependent Claim
375 words
A semiconductor memory including a plurality of memory cells arranged in a matrix with each of said memory cells being coupled to one of a plurality of first word lines for said memory, one of a plurality of second word lines for said memory and one of a plurality of bit lines for said memory, and further including a semiconductor substrate having a first conductivity type and at least first and second surface regions that are disposed in adjacent portions of said substrate, wherein said first and second surface regions are separated from one another by an oxide film for isolation, wherein each of said first and second surface regions has a memory cell formed therein, and wherein each of said memory cells comprises: an insulated-gate field effect transistor having a source and drain region formed by semiconductor regions in a semiconductor layer over said substrate, a first insulating film formed on a surface region of said semiconductor layer which is disposed between source and drain regions, and a gate electrode formed on said first insulating film connected to said first line; and a memory element formed on said semiconductor substrate adjacent to said insulated-gage field effect transistor having a source and drain region formed by semiconductor regions in said substrate, wherein one of said source or drain regions of said memory element is connected to said bit lines, and the other of said drain or source regions of said memory element is connected to a predetermined potential, a second insulating film formed on a surface region of said semiconductor substrate between said source and drain regions of said memory element, wherein said semiconductor layer extends over said second insulating film to form a first electrode serving as a floating gate of said memory element connected to one of said drain or source regions of said insulated-gate field effect transistor, a third insulating film formed on said first electrode, and a second electrode serving as a control gate of said memory element formed on said third insulating film connected to said second word line, wherein said insulated-gate field effect transistor is formed so that said source and drain thereof and a channel region extending between said source and drain are formed on said oxide film.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-04-06 | 1990-10-06 | 1991-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-06 | 1994-10-06 | 1995-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-06 | 1998-10-06 | 1999-04-07 | $7700.00 | Window Closed / Lapsed |