Insulated gate transistor having reduced channel length

Claim 2

An insulated gate static induction transistor comprising: a semiconductor substrate; a source region and a drain region formed in a surface of said semiconductor substrate, said source and drain regions having high impurity concentrations; a channel region formed on said substrate extending between said source region and said drain region, said channel region having a length of 1 μm or less and a low impurity concentration of 1×10 15 cm -3 or less, said length and said impurity concentration permitting punch-through between said source and drain regions; a high impurity concentration region having a conductivity type opposite to that of said source region formed beneath said channel region; a gate insulating layer extending into said channel region farther inwardly of said substrate than said source region and having a substantially flat inward surface parallel to said substrate surface, said source and drain regions defining a controlled current path therebetween through an internal portion of said channel region; and a gate electrode positioned on the flat surface of said gate insulating layer, wherein diffusion potentials of said substrate, said gate electrode and said source region provide a normally off characteristic, and wherein an exponential relationship exists between a non-saturating drain current characteristic and a drain voltage characteristic.

Claim 3

The insulated gate transistor of claim 1, wherein said source region is an n + region, and said gate electrode is made of p + polycrystalline silicon.

Claim 4

The insulated gate transistor of claim 2, wherein said gate electrode is overlaid with a material selected from the group consisting of silicides and metals.

Claim 5

The insulated gate transistor of claim 2, wherein said gate electrode is overlaid with a layer of annealed, boron-doped, silicon-rich molybdenum silicide.

Claim 6

The insulated gate transistor of claim 1, wherein said gate electrode is made of a material selected from the group consisting of Al, AlSi, AlSi 2 , W, Mo, Pt, MoSi 2 , WSi 2 , TaSi 2 , TiSi 2 , CoSi 2 , NiSi 2 , Pd 2 Si and PtSi.

Claim 7

The insulated gate transistor of claim 1, wherein said source of region is formed by a method comprising the steps of: forming a layer of molybdenum or tungsten on said channel region; injecting impurity ions in a high concentration through said molybdenum or tungsten layer to convert portions of said channel region beneath said molybdenum or tungsten layer to an amorphous or near-amorphous state; and heating the device thereby formed.

Claim 8

The insulated gate transistor of claim 6, wherein said layer of molybdenum or tungsten has a thickness in a range of about 100 to several hundered angstroms, said impurity comprises arsenic, said impurity ions are implanted in a dose in a range of 1×10 15 to 1×10 16 cm -2 , and a depth of said portions of said channel region converted to an amorphous or near-amorphous state is equal to or slightly greater than said thickness of said molybdenum or tungsten layer.

Claim 9

The insulated gate transistor of claim 1, wherein: ##EQU4## wherein L is an effective length of a channel between said source and drain regions and D is a depth of said channel region.

Claim 10

The insulated gate transistor of claim 1, wherein said source and drain regions have substantially equal depths.

Claim 11

The insulated gate transistor of claim 1, wherein said drain region is deeper than said source region.

Claim 12

The insulated gate transistor of claim 10, wherein said drain region extends past said channel region to said substrate.

Claim 13

A dynamic random access memory, said memory comprising a plurality of memory cells, each of said memory cells comprising an insulated gate static induction transistor, including: a semiconductor substrate; a source region and a drain region formed in a surface of said semiconductor substrate, said source and drain regions having a high impurity concentration; a channel region formed on said substrate extending between said source region and said drain region, said channel region having a length of 1 μm or less and a low impurity concentration of 1×10.sup.. cm -3 or less, said length and said impurity concentration permitting punch-through between said source and drain regions, and said drain region extending past said channel region to said substrate; a gate insulating layer extending into said channel region farther inwardly of said substrate than said source region and having a substantially flat inward surface parallel to said substrate surface; a gate electrode positioned on the flat surface of said gate insulating layer, diffusion potentials of said substrate, said gate electrode and said source region providing a normally off characteristic; and wherein an exponential relationship exists between a non-saturating drain current characteristic and a drain voltage characteristic; said source and drain regions defining a controlled current path therebetween through an internal portion of said source region; a conductive region in contact with said drain region; a polycrystalline silicon region in contact with said conductive region; a thin insulating layer formed over said polycrystalline silicon region; and a metal or low resistivity polycrystalline silicon electrode formed over said thin insulating layer.

Claim 14

A dynamic random access memory, said memory comprising a plurality of memory cells, each of said memory cells comprising an insulated gate static induction transistor, including: a semiconductor substrate; a source region and a drain region formed in a surface of said semiconductor substrate, said source and drain regions having a high impurity concentration; a channel region formed on said substrate extending between said source region and said drain region, said channel region having a length of 1 μm or less and a low impurity concentration of 1×10.sup.. cm -3 or less, said length and said impurity concentration permitting punch-through between said source and drain regions, and said drain region extending past said channel region to said substrate; a gate insulating layer extending into said channel region farther inwardly of said substrate than said source region and having a substantially flat inward surface parallel to said substrate surface; a gate electrode positioned on the flat surface of said gate insulating layer, diffusion potentials of said substrate, said gate electrode and said source region providing a normally off characteristic; and wherein an exponential relationship exists between a non-saturating drain current characteristic and a drain voltage characteristic; said source and drain regions defining a controlled current path therebetween through an internal portion of said source region; a conductive region in contact with said drain region; a polycrystalline silicon region in contact with said conductive region; a thin insulating layer formed over said polycrystalline silicon region; and a metal or low resistivity polycrystalline silicon electrode formed over said thin insulating layer.

Claim 15

The memory device of claim 12, wherein said thin insulating layer is made of a material selected from the group consisting of SiO 2 , Si 3 N 4 and SiO x N y .

Claim 16

The memory device of claim 12, wherein said thin insulating layer is made of Ta 2 O 5 .

Claim 17

The memory device of claim 12, wherein said conductive region is made of a material selected from the group consisting of polycrystalline silicon, tantalum and aluminum.

Claim 18

The memory device of claim 12, wherein at least one of said drain region and said substrate has an impurity concentration of not more than about 2×10 17 cm -3 .

Claim 19

The memory device of claim 12, wherein said substrate comprises a p + layer directly beneath said channel region and in contact with said drain region, and a p - layer beneath said p + layer.

Claim 20

A complementary MOS transistor device comprising: a semiconductor substrate of a conductivity type; first and second insulated gate static induction transistors formed in said semiconductor substrate, said first and second insulated gate transistors being of opposite conductivity types, each of said insulated gate static induction transistors comprising: a source region and a drain region formed in a surface of said semiconductor substrate, said source and drain regions having a high impurity concentration; a channel region formed on said substrate extending between said source region and said drain region, said channel region having a length of 1 μm or less and a low impurity concentration of 1×10 15 cm -3 or less, said length and said impurity concentration permitting punch-through between said source and drain regions; a high impurity concentration region having a conductivity type opposite to that of said source region formed beneath said channel region; said source and drain regions defining a controlled current path therebetween through an internal portion of said source region; a gate insulating layer extending into said channel region farther inwardly of said substrate than said source region and having a substantially flat inward surface parallel to said substrate surface; and a gate electrode positioned on the flat surface of said gate insulating layer, wherein diffusion potentials of said substrate, said gate electrode and said source region provide a normally off characteristic, and wherein an exponential relationship exists between a non-saturating drain current characteristic and a drain voltage characteristic; and wherein said second insulated gate transistor as said high impurity concentration region a layer disposed between said channel region of said second insulated gate transistor and said substrate of a conductivity type opposite said conductivity type of said substrate.

Claim 21

A complementary MOS transistor device comprising: a semiconductor substrate of a conductivity type; first and second insulated gate static induction transistors formed in said semiconductor substrate, said first and second insulated gate transistors being of opposite conductivity types, each of said insulated gate static induction transistors comprising: a source region and a drain region formed in a surface of said semiconductor substrate, said source and drain regions having a high impurity concentration; a channel region formed on said substrate extending between said source region and said drain region, said channel region having a length of 1 μm or less and a low impurity concentration of 1×10 15 cm -3 or less, said length and said impurity concentration permitting punch-through between said source and drain regions; a high impurity concentration region having a conductivity type opposite to that of said source region formed beneath said channel region; said source and drain regions defining a controlled current path therebetween through an internal portion of said source region; a gate insulating layer extending into said channel region farther inwardly of said substrate than said source region and having a substantially flat inward surface parallel to said substrate surface; and a gate electrode positioned on the flat surface of said gate insulating layer, wherein diffusion potentials of said substrate, said gate electrode and said source region provide a normally off characteristic, and wherein an exponential relationship exists between a non-saturating drain current characteristic and a drain voltage characteristic; and wherein said second insulated gate transistor as said high impurity concentration region a layer disposed between said channel region of said second insulated gate transistor and said substrate of a conductivity type opposite said conductivity type of said substrate.

Claim 22

The complementary MOS device of claim 18, further comrising an insulating region separating said drain region of said first insulated gate transistor from said drain region of said second insulated gate transistor.

Claim 23

The complementary MOS device of claim 18, wherein said drain of said first insulated gate transistor extends into contact with said drain of said second insulated gate transistor.

Claim 24

The complementary MOS device of claim 19, further comprising a thin silicide region covering said drain region of said first insulated gate transistor and said drain region of said second insulated gate transistor.

Claim 25

The complementary MOS device of claim 18, wherein said gate electrode of said first and second insulated gate transistors is made of a material selected from the group consisting of Al, AlSi, AlCu, W, Mo, Pt, MoSi 2 , WSi 2 , TiSi 2 , TaSi 2 , PtSi, NiSi 2 and Pd 2 Si.