Voltage level shifter

Claim 2

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively turning on to connect said second input and said first output transistors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off said first and second reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, said control means including means for thereafter turning on said one input transistor and said first and second reset transistors to effectuate a change of output logic state.

Claim 3

The voltage level shifter of claim 1, wherein said control means includes means for periodically turning off said first and second input transistors for a predefined time and turning off said reset transistors for at least a portion of said time, said control means including means for thereafter allowing the input transistors to respond to the logic states of said input signal.

Claim 4

The voltage level shifter of claim 1, wherein said control means includes: means for periodically generating a reset control signal; a first reset control transistor connected to said first reset transistor for turning on in response to the second logic state of said input signal and thereby turning on said first reset transistor; a second reset control transistor connected to said second reset transistor for turning on in response to the first logic state of said input signal and thereby turning on said second reset transistor; a third reset control transistor connected to said first reset transistor for turning the first reset transistor off in response to said reset control signal; a fourth reset control transistor connected to said second reset transistor for turning the second reset transistor off in response to said reset control signal; and means for turning off said first and second input transistors and said first and second reset control transistors when said reset control signal is generated.

Claim 5

The voltage level shifter of claim 3, wherein said first and second input transistors and said first and second reset control transistors are P-type field-effect transistors and said output, reset and third and fourth reset control transistors are N-type field-effect transistors.

Claim 6

The voltage level shifter of claim 4, wherein said P-type transistors have a Z/L ratio of 10/5 and the N-type transistors have a Z/L ratio of 5/5.

Claim 7

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively truning on to connect said second input and said first output transistiors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off said first and second reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, said control means including means for thereafter turning on said one input transistor and at least one of said reset treansistors so that the output transistor which was turned off and the other input transistor which was turned on prior to the change of logic state of the input signal are connected to effectuate a change of output logic state.

Claim 8

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively truning on to connect said second input and said first output transistiors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off said first and second reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, said control means including means for thereafter turning on said one input transistor and at least one of said reset treansistors so that the output transistor which was turned off and the other input transistor which was turned on prior to the change of logic state of the input signal are connected to effectuate a change of output logic state.

Claim 9

The voltage level shifter of claim 6, wherein said control means includes means for periodically turning off said first and second input transistors for a predefined time and turning off said reset transistors for at least a portion of said time, said control means including means for thereafter allowing the input transistors to respond to the logic states of said input signal.

Claim 10

The voltage level shifter of claim 6, wherein said control means includes: means for periodically generating a reset control signal; a first reset control transistor connected to said first reset transistor forturning on in response to the second logic state of said input signal and thereby turning on said first reset transistor; a second reset control transistor connected to said second reset transistor for turning on in response to the first logic state of said input signal and thereby turning on said second reset transistor; a third reset control transistor connected to said first reset transistor for turning the first reset transistor off in response to said reset control signal; a fourth reset control transistor connected to said second reset transistor for turning the second reset transistor off in response to said reset control signal; and means for turning off said first and second input transistors and said first and second reset control transistors when said reset control signal is generated.

Claim 11

The voltage level shifter of claim 8, wherein said first and second input transistors and said first and second reset control transistors are P-type field-effect transistors and said output, reset and third and fourth reset control transistors are N-type filed-effect transistors.

Claim 12

The voltage level shifter of claim 9, wherein said P-type transistors have a Z/L ratio of 10/5 and the N-type transistors have a Z/L ratio of 5/5.

Claim 13

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively turning on to connect said second input and said first output transistors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off at least one of said reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, so that the output transistor which is turned on and said one input transistor which is turned off prior to said change in logic state are disconnected; said control means including means for thereafter turning on said one input transistor and said first and second reset transistors to effectuate an output logic state change.

Claim 14

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively turning on to connect said second input and said first output transistors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off at least one of said reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, so that the output transistor which is turned on and said one input transistor which is turned off prior to said change in logic state are disconnected; said control means including means for thereafter turning on said one input transistor and said first and second reset transistors to effectuate an output logic state change.

Claim 15

The voltage level shifter of claim 11, wherein said control means includes means for periodically turning off said first and second input transistors for a predefined time and turning off said reset transistors for at least a portion of said time, said control means including means for thereafter allowing the input transistors to respond to the logic states of said input signal.

Claim 16

The voltage level shifter of claim 11, wherein said control means includes: means for periodically generating a reset control signal; a first reset control transistor connected to said first reset transistor for turning on in response to the second logic state of said input signal and thereby turning on said first reset transistor; a second reset control transistor connected to said second reset transistor for turning on in response to the first logic state of said input signal and thereby turning on said second reset transistor; a third reset control transistor connected to said first reset transistor for turning the first reset transistor off in response to said reset control signal; a fourth reset control transistor connected to said second reset transistor for turning the second reset transistor off in response to said reset control signal; and means for turning off said first and second input transistors and said first and second reset control transistors when said reset control signal is generated.

Claim 17

The voltage level shifter of claim 13, wherein said first and second input transistors and said first and second reset control transistors are P-type field-effect transistors and said output, reset and third and fourth reset control transistors are N-type field-effect transistors.

Claim 18

The voltage level shifter of claim 14 wherein said P-type transistors have a Z/L ratio of 10/5 and the N-type transistors have a Z/L ratio of 5/5.

Claim 19

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively turning on to connect said second input and said first output transistors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off one of said reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, so that the output transistor which is turned on and said one input transistor which is turned off prior to said change in logic state are disconnected, said control means including means for thereafter turning on said one input transistor and the other of said reset transistors, so that the output transistor which was turned off and the input transistor which was turned on prior to the change of state of the input signal are connected to effectuate a change of output logic state.

Claim 20

A voltage level shifter for receiving an input signal having a predetermined magnitude of voltage and generating an output signal having a different magnitude of voltage, comprising: a first input transistor for turning on to conduct in response to a first of two logic states of said input signal and for turning off in response to the second of said logic states; a second input transistor for turning on to conduct in response to the second of said two logic states of said input signal and for turning off in response to the first of said logic states; a first output transistor connected to said first input transistor for turning on to conduct when said first input transistor is conducting and for generating said output signal at the point of connection of the transistors; a second output transistor connected to said second input transistor for turning on to conduct when said second input transistor is conducting and for generating the inverse of said output signal at the point of connection of the transistors; a first reset transistor connected between said first input transistor and said second output transistor for selectively turning on to connect said first input and said second output transistors and for selectively turning off to disconnect the first input and second output transistors; a second reset transistor connected between said second input transistor and said first output transistor for selectively turning on to connect said second input and said first output transistors and for selectively turning off to disconnect said second input and first output transistors; and control means for turning off one of said reset transistors prior to turning on one of said input transistors in response to a change in the logic state of said input signal, so that the output transistor which is turned on and said one input transistor which is turned off prior to said change in logic state are disconnected, said control means including means for thereafter turning on said one input transistor and the other of said reset transistors, so that the output transistor which was turned off and the input transistor which was turned on prior to the change of state of the input signal are connected to effectuate a change of output logic state.

Claim 21

The voltage level shifter of claim 16, wherein said control means includes means for periodically turning off said first and second input transistors for a predefined time and turning off said reset transistors for at least a portion of said time, said control means including means for thereafter allowing the input transistors to respond to the logic states of said input signal.

Claim 22

The voltage level shifter of claim 16, wherein said control means includes: means for periodically generating a reset control signal; a first reset control transistor connected to said first reset transistor for turning on in response to the second logic state of said input signal and thereby turning on said first reset transistor; a second reset control transistor connected to said second reset transistor for turning on in response to the first logic state of said input signal and thereby turning on said second reset transistor; a third reset control transistor connected to said first reset transistor for turning the first reset transistor off in response to said reset control siganl; a fourth reset control transistor connected to said second reset transistor for turning the second reset transistor off in response to said reset control signal; and means for turning off said first and second input transistors and said first and second reset control transistors when said reset control signal is generated.

Claim 23

The voltage level shifter of claim 18, wherein said first and second input transistors and said first and second reset control transistors are P-type field-effect transistors and said output, reset and third and fourth reset control transistors are N-type field-effect transistors.

Claim 24

The voltage level shifter of claim 19, wherein said P-type transistors have a Z/L ratio of 10/5 and the N-type transistors have a Z/L ratio of 5/5.