US4663742A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Directory memory system having simultaneous write, compare and bypass capabilites
Assignee: International Business Machines Corp
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Filing: 1984-10-30
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Granted: 1987-05-05
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Expires: 2004-10-30
Abstract
Abstract A directory memory system including a plurality of reconfigurable subarrays of memory cells and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays. Output data from the subarrays is connected to compare data logic for comparing the subarray data to one or more bytes of compare input data, and to bit select logic for selectively placing the subarray data onto an output bus. Bypass select logic causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays, and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays while simultaneously performing the compare or the compare/bypass operation.
Inventors
- 👤 John E. Andersen
- 👤 Robert L. Barry
- 👤 Kenneth H. Christie
- 👤 Dennis J. Shea
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:05
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
146 words
An integrated circuit memory system comprising: an array of memory cells divided into a plurality of subarrays; sense amplifier means for sensing the contents of selected cells in said subarrays; compare logic means connected to said sense amplifier means for comparing the contents of said selected cells in said subarrays with compare input data; data output means connected to said sense amplifier means; decode means connected to said sense amplifier means for connecting the output of a selected one of said subarrays to said data output means; a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected of said subarrays and compared with said compare input data.
Claim 2
Dependent Claim
146 words
An integrated circuit memory system comprising: an array of memory cells divided into a plurality of subarrays; sense amplifier means for sensing the contents of selected cells in said subarrays; compare logic means connected to said sense amplifier means for comparing the contents of said selected cells in said subarrays with compare input data; data output means connected to said sense amplifier means; decode means connected to said sense amplifier means for connecting the output of a selected one of said subarrays to said data output means; a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected of said subarrays and compared with said compare input data.
Claim 3
Dependent Claim
47 words
The memory system of claim 1, further comprising: mode select means connected to said plurality of write data input means, wherein selected portions of said array input data may be replicated at the outputs of said write data input means and written into selected of said subarrays.
Claim 4
Dependent Claim
72 words
The memory system of claim 2, further comprising: bypass means for electrically disconnecting said sense amplifier means from said data output means and for electrically connecting selected portions of said compare input data to said data output means, wherein said selected portions of said compare input data are outputted from said data output means while other selected portions of said compare input data are simultaneously compared with selected cells of a subarray.
Claim 5
Dependent Claim
58 words
The memory system of claim 3, further comprising: a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected subarrays.
Claim 6
Dependent Claim
45 words
The memory system of claim 4, further comprising: mode select means connected to said plurality of write data input means, wherein selected portions of said array input data may be replicated at the outputs of said write data input means and written into selected subarrays.
Claim 7
Dependent Claim
103 words
An integrated circuit memory system comprising: an array of memory cells; sense amplifier means for sensing the contents of selected cells in said array; data output means connected to said sense amplifier means; compare logic means connected to said sense amplifier means and to said data output means for comparing the contents of said selected cells in said array with compare input data; and bypass means for electrically disconnecting said sense amplifier means from said data output means and for electrically connecting said compare input data to said data output means, wherein said compare input data is outputted from said data output means.
Claim 8
Dependent Claim
103 words
An integrated circuit memory system comprising: an array of memory cells; sense amplifier means for sensing the contents of selected cells in said array; data output means connected to said sense amplifier means; compare logic means connected to said sense amplifier means and to said data output means for comparing the contents of said selected cells in said array with compare input data; and bypass means for electrically disconnecting said sense amplifier means from said data output means and for electrically connecting said compare input data to said data output means, wherein said compare input data is outputted from said data output means.
Claim 9
Dependent Claim
45 words
The memory system of claim 6 wherein said array of memory cells is divided into a plurality of subarrays, further comprising: decode means connected to said sense amplifier means for connecting the output of a selected one of said subarrays to said data output means.
Claim 10
Dependent Claim
58 words
The memory system of claim 7, further comprising: a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected subarrays.
Claim 11
Dependent Claim
45 words
The memory system of claim 8, further comprising: mode select means connected to said plurality of write data input means, wherein selected portions of said array input data may be replicated at the outputs of said write data input means and written into selected subarrays.
Claim 12
Dependent Claim
130 words
An integrated circuit memory system comprising: an array of memory cells; sense amplifier means for sensing the contents of selected cells in said array; data output means connected to said sense amplifier means; compare logic means connected to said sense amplifier means and to said data output means for comparing the contents of said selected cells in said array with compare input data; and bypass means for electrically disconnecting said sense amplifier means from said data output means and for electrically connecting selected portions of said compare input data to said data output means, wherein said selected portions of said compare input data are outputted from said data output means while other selected portions of said compare input data are simultaneously compared with said selected cells of said memory array.
Claim 13
Dependent Claim
130 words
An integrated circuit memory system comprising: an array of memory cells; sense amplifier means for sensing the contents of selected cells in said array; data output means connected to said sense amplifier means; compare logic means connected to said sense amplifier means and to said data output means for comparing the contents of said selected cells in said array with compare input data; and bypass means for electrically disconnecting said sense amplifier means from said data output means and for electrically connecting selected portions of said compare input data to said data output means, wherein said selected portions of said compare input data are outputted from said data output means while other selected portions of said compare input data are simultaneously compared with said selected cells of said memory array.
Claim 14
Dependent Claim
45 words
The memory system of claim 10 wherein said array of memory cells is divided into a plurality of subarrays, further comprising: decode means connected to aid sense amplifier means for connecting the output of a selected one of said subarrays to said data output means.
Claim 15
Dependent Claim
58 words
The memory system of claim 11, further comprising: a plurality of write data input means each connected to array input data and to at least two of said subarrays; and a plurality of write select means each connected to one of said subarrays, wherein selected portions of said array input data may be simultaneously written into selected subarrays.
Claim 16
Dependent Claim
45 words
The memory system of claim 12, further comprising: mode select means connected to said plurality of write data input means, wherein selected portions of said array input data may be replicated at the outputs of said write data input means and written into selected subarrays.
References Cited (Backward Citations)
US3238510A
Cited
US3471838A
Cited
US3685020A
Cited
US3686640A
Cited
US3761898A
Cited
US3761881A
Cited
US3723976A
Cited
US3800289A
Cited
US3787817A
Cited
US4087853A
Cited
US3858187A
Cited
US3958222A
Cited
US3906458A
Cited
US4044338A
Cited
US3967251A
Cited
US4075686A
Cited
US4070657A
Cited
US4136385A
Cited
US4286173A
Cited
US4219883A
Cited
US4138738A
Cited
US4238841A
Cited
US4268907A
Cited
US4222112A
Cited
US4241425A
Cited
US4332010A
Cited
US4460984A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-04 | 1990-11-03 | 1991-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-04 | 1994-11-03 | 1995-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-04 | 1998-11-03 | 1999-05-05 | $7700.00 | Window Closed / Lapsed |