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US4665381A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital-to-analog converter

Assignee: Toshiba Corp
•
Filing: 1984-04-17
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Granted: 1987-05-12
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Expires: 2004-04-17
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Abstract

Abstract In a D/A converter, a reference voltage is divided into a plurality of divided voltages by a plurality of resistors connected in series. The divided voltages are respectively selected by switches which are turned on according to the contents of a digital input. With the use of an expanding bit or bits, a plurality of the switches are simultaneously turned on.

Inventors

  • 👤 Eiji Masuda
  • 👤 Yasuhiko Fujita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 21:48
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/80; H03M1/808; H03M1/12; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 279 words
A digital-analog converter, coupled to sources of high and low potential, for converting a digital input of having n bits into an analog output voltage, said n-bit digital input including a first group of higher order bits and a second group of lower order bits and said converter comprising: an input terminal receiving said n-bit digital input; an output terminal presenting said analog output voltage; a first number of resistors serially connected between said sources of high and low potential such that junctions at which said resistors are connected have potential values determined by a ratio of resistance values of said resistors, said first number of said resistors being less than 2 n-1 ; a second number of switches each connected between a different one of said junctions of said resistors and said output terminal, said second number also being less than 2 n-1 ; and decoder circuit means, connected to said input terminal and to said switches, for receiving said n-bit binary input and for rendering selected ones of said switches conductive according to said first group of bits, said decoder circuit means including first selection means, responsive to said second group of bits being in a specified state, for rendering conductive one of said second switches corresponding to said first group of bits when said second group of bits is in said specified state, and second selection means, responsive to said second group of bits, for rendering conductive said one switch corresponding to said first group of bits and at least one other of said switches corresponding to said first and second input bit groups when the second input bit group is not in said specified state.
Claim 2
Dependent Claim 279 words
A digital-analog converter, coupled to sources of high and low potential, for converting a digital input of having n bits into an analog output voltage, said n-bit digital input including a first group of higher order bits and a second group of lower order bits and said converter comprising: an input terminal receiving said n-bit digital input; an output terminal presenting said analog output voltage; a first number of resistors serially connected between said sources of high and low potential such that junctions at which said resistors are connected have potential values determined by a ratio of resistance values of said resistors, said first number of said resistors being less than 2 n-1 ; a second number of switches each connected between a different one of said junctions of said resistors and said output terminal, said second number also being less than 2 n-1 ; and decoder circuit means, connected to said input terminal and to said switches, for receiving said n-bit binary input and for rendering selected ones of said switches conductive according to said first group of bits, said decoder circuit means including first selection means, responsive to said second group of bits being in a specified state, for rendering conductive one of said second switches corresponding to said first group of bits when said second group of bits is in said specified state, and second selection means, responsive to said second group of bits, for rendering conductive said one switch corresponding to said first group of bits and at least one other of said switches corresponding to said first and second input bit groups when the second input bit group is not in said specified state.
Claim 3
Dependent Claim 26 words
A digital-analog converter according to claim 1 wherein each of said switches has an ON resistance greater than the resistance value of any of said resistors.
Claim 4
Dependent Claim 21 words
A digital-analog converter according to claim 1 wherein said first number and said second number are equal to 2 n-1 .
Claim 5
Dependent Claim 21 words
A digital-analog converter according to claim 1 wherein said first number and said second number are equal to 2 n-2 .

References Cited (Backward Citations)

US3705359A Cited
US3812478A Cited
US4160244A Cited
US4363024A Cited
US4338591A Cited
US4491825A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-05-11 1990-11-10 1991-05-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-05-11 1994-11-10 1995-05-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-05-11 1998-11-10 1999-05-12 $7700.00 Window Closed / Lapsed

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