US4665480A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system which permits of using the same erasable and programmable memory for instructions and data both in reading and writing
Assignee: US Philips Corp
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Filing: 1986-06-26
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Granted: 1987-05-12
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Expires: 2006-06-26
Abstract
Abstract The data processing system according to the invention has a microprocessor and an external erasable and programmable memory. A logic connection system is arranged between control pins of the microprocessor and a controlled pin of the external memory. These control pins of the microprocessor are the program control pin, a port control pin, the controlled pin of the memory and the memory selection pin. This ligic connection system permits using only one memory both for reading and writing of instructions and/or data instead of the two memories generally used.
Inventors
- 👤 Serge Robert
- 👤 Pierre Fevrier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:09
CPC Classifications
G; G06; G06Q; G06Q40/00; G06Q40/02; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/32
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
191 words
A data processing system comprising a non-volatile external memory and a microprocessor with an internal memory, the microprocessor and the non-volatile external memory being connected to a bus, said microprocessor comprising a program control pin and at least one port control pin, said non-volatile external memory comprising a memory selection pin, characterized in that said external memory is an erasable and programmable memory said memory selection pin of which is connected to a first output of a logic connection system, this logic connection system having a first input connected to the said program control pin and a second input connected to one of said port control pins, which logic connection system being arranged on the one hand for transmitting to its first output a signal present at its first input during an operation of reading the non-volatile external memory controlled by the microprocessor and on the other hand for transmitting to its first output the signal present at its second input during an operation of writing in said non-volatile external memory controlled by the microprocessor and stopping a propagation of said signal present at its second input to the first input.
Claim 2
Dependent Claim
191 words
A data processing system comprising a non-volatile external memory and a microprocessor with an internal memory, the microprocessor and the non-volatile external memory being connected to a bus, said microprocessor comprising a program control pin and at least one port control pin, said non-volatile external memory comprising a memory selection pin, characterized in that said external memory is an erasable and programmable memory said memory selection pin of which is connected to a first output of a logic connection system, this logic connection system having a first input connected to the said program control pin and a second input connected to one of said port control pins, which logic connection system being arranged on the one hand for transmitting to its first output a signal present at its first input during an operation of reading the non-volatile external memory controlled by the microprocessor and on the other hand for transmitting to its first output the signal present at its second input during an operation of writing in said non-volatile external memory controlled by the microprocessor and stopping a propagation of said signal present at its second input to the first input.
Claim 3
Dependent Claim
23 words
A data processing system as claimed in claim 1, characterized in that said non-volatile external memory is an electrically erasable and programmable memory.
Claim 4
Dependent Claim
65 words
A data processing system as claimed in claim 1, the non-volatile external memory of which comprises an output control pin, characterized in that the said logic connection system comprises a second output, which is connected to said first input for directly transmitting the signal present at said first input, said output control pin of the non-volatile external memory being connected to the said second output.
Claim 5
Dependent Claim
60 words
A data processing system as claimed in claim 1, the said port control pin of which can be utilized so as to be operated in a time multiplex mode at the output of said microprocessor, characterized in that said logic connection system is also arranged to prevent a signal present at its first input from interfering with said second input.
Claim 6
Dependent Claim
23 words
A data processing system as claimed in claim 1, characterized in that said logic connection system is constituted by a logic AND gate.
Claim 7
Dependent Claim
28 words
A data processing system as claimed in claim 4, characterized in that the said logic connection system comprises at least two diodes arranged according to a wired AND.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-11 | 1990-11-10 | 1991-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-11 | 1994-11-10 | 1995-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-11 | 1998-11-10 | 1999-05-12 | $7700.00 | Window Closed / Lapsed |