US4670877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
LSI circuit with self-checking facilitating circuit built therein
Assignee: Toshiba Corp
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Filing: 1984-09-21
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Granted: 1987-06-02
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Expires: 2004-09-21
Abstract
Abstract According to this invention, an LSI circuit is provided with a pseudorandom data generating circuit for producing pseudorandom data and a timing signal generating circuit for producing test timing signals in synchronism with a control input timing signal necessary for the operation of an internal logic circuit. The LSI circuit has two input lines, a control input line and a data input line. The LSI circuit further includes a circuit, which selectively supplies the timing signals from the timing signal generating circuit on the control input line and selectively supplies the pseudorandom data from the psuedorandom data generating circuit on the data input line. Consequently, the LSI circuit automatically generates control input signals and data input signals within itself to carry out the self-checking operation.
Inventors
- 👤 Shinji Nishibe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
168 words
An LSI circuit having built-in self-checking comprising: an internal logic circuit; a data bus for supplying data to said internal logic circuit; a control bus for supplying a control signal to said internal logic circuit; pseudorandom data generator means for generating psuedorandom data to be supplied to said internal logic circuit via said data bus; timing signal generator means for supplying a test timing signal, having the same timing as a timing signal which would be used when said internal logic circuit is actually used, to said internal logic circuit via said control bus; and switching means, connected to both said timing signal generator means and said pseudorandom data generator means, for switching between the output signal from said timing signal generator means and an externally supplied control input signal, to selectively supply to said internal logic circuit either the output signal from said timing signal generator means and the output signal from said pseudorandom data generator means or the control input signal and the data input signal.
Claim 2
Dependent Claim
168 words
An LSI circuit having built-in self-checking comprising: an internal logic circuit; a data bus for supplying data to said internal logic circuit; a control bus for supplying a control signal to said internal logic circuit; pseudorandom data generator means for generating psuedorandom data to be supplied to said internal logic circuit via said data bus; timing signal generator means for supplying a test timing signal, having the same timing as a timing signal which would be used when said internal logic circuit is actually used, to said internal logic circuit via said control bus; and switching means, connected to both said timing signal generator means and said pseudorandom data generator means, for switching between the output signal from said timing signal generator means and an externally supplied control input signal, to selectively supply to said internal logic circuit either the output signal from said timing signal generator means and the output signal from said pseudorandom data generator means or the control input signal and the data input signal.
Claim 3
Dependent Claim
38 words
An LSI circuit according to claim 1, further comprising an output data compressor, coupled to the output side of said internal logic circuit, for observing the output of said internal logic circuit for vertification of said LSI cirucit.
Claim 4
Dependent Claim
32 words
An LSI circuit according to claim 1 further comprising means for supplying data to said timing signal generator means indicating the type of timing signal that said timing signal generator should output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |