US4672354A
Expired / Lapsed
US
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Fabrication of dielectrically isolated fine line semiconductor transducers and apparatus
Assignee: Kulite Semiconductor Products Inc
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Filing: 1985-12-05
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Granted: 1987-06-09
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Expires: 2005-12-05
Abstract
Abstract There is disclosed apparatus and methods of fabricating a piezoresistive semiconductor structure for use in a transducer. According to one method, a layer of silicon dioxide is grown over the surface of a first semiconductor wafer which is designated as a carrier wafer. A layer of glas is then formed on the top surface of the carrier wafer over said layer of silicon dioxide. A second wafer has diffused therein a high conductivity semiconductor layer which is diffused on a top surface of a sacrificial semiconductor wafer. The first and second wafers are then bonded together by means of an electrostatic bond with the high conductivity layer of the sacrificial wafer facing the glass layer of the first wafer. After securing the wafers together, one may etch away the remaining portion of the sacrificial wafer to provide a high conductivity resistive layer which is secured to the glass layer of the first wafer and is patterned to form a resistive network using standard photolithographic making. In another embodiment, the sacrificial wafer is processed by means of a high conductivity diffusion procedure whereby a resistive line pattern is formed in the second wafer. After diffusion, the second wafer is etched so that the high conductivity pattern projects from the top surface. This top surface consisting of the projected high conductivity resistive pattern is then bonded to the glass layer of the second wafer. After bonding the two wafers together, the unwanted N-type regions of the sacrificial wafer are etched away using a conductivity selective etch to form the resistive pattern.
Inventors
- 👤 Anthony D. Kurtz
- 👤 Timothy A. Nunn
- 👤 Richard A. Weber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:31
CPC Classifications
G; G01; G01L; G01L1/00; G01L1/20; G01L1/22; G01L1/2287; G01L1/2293; G01L9/00; G01L9/0041; G01L9/0042; Y; Y10; Y10S; Y10S73/00; Y10S73/04; Y10T; Y10T29/00; Y10T29/42; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49103
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
113 words
A method of fabricating a piezoresistive semiconductor structure for use in a transducer comprising the steps of: (a) growing an insulating layer of a silicon compound over the surface of a first semiconductor wafer, (b) forming a layer of borosilicate glass on a top surface of said first wafer over said grown silicon compound, (c) diffusing a high conductivity semiconductor layer on a surface of a second semiconductor wafer, (d) electrostatically bonding said glass layer of said first wafer to said high conductivity layer of said second wafer, (e) etching away the remaining portion of said second wafer to provide a high conductivity layer secured to said glass layer of said first wafer.
Claim 2
Independent Claim
113 words
A method of fabricating a piezoresistive semiconductor structure for use in a transducer comprising the steps of: (a) growing an insulating layer of a silicon compound over the surface of a first semiconductor wafer, (b) forming a layer of borosilicate glass on a top surface of said first wafer over said grown silicon compound, (c) diffusing a high conductivity semiconductor layer on a surface of a second semiconductor wafer, (d) electrostatically bonding said glass layer of said first wafer to said high conductivity layer of said second wafer, (e) etching away the remaining portion of said second wafer to provide a high conductivity layer secured to said glass layer of said first wafer.
Claim 3
Dependent Claim
61 words
The method according to claim 1, further including the step of forming a resistor pattern in said high conductivity layer prior to binding said glass layer to said second wafer, and etching said second wafer about said pattern to cause said pattern to project from the surface of said second wafer to thereby bond said glass layer to said projecting areas.
Claim 4
Dependent Claim
25 words
The method according to claim 1, further including the step of forming a resistive pattern on said high conductivity layer secured to said glass layer.
Claim 5
Dependent Claim
38 words
The method according to claim 1, further including the step of forming an aperture in said first semiconductor wafer on a surface opposite to that surface containing said glass layer with said aperture defining an active diaphragm region.
Claim 6
Dependent Claim
28 words
The method according to claim 1, wherein said high conductivity layer is a P-type layer of high concentration with said semiconductor wafer being a lower conductivity N-type wafer.
Claim 7
Dependent Claim
42 words
The method according to claim 1, wherein said step of growing a layer of a silicon compound includes growing a layer of silicon dioxide on said first wafer and then depositing a layer of glass over a surface of said first wafer.
Claim 8
Dependent Claim
28 words
The method according to claim 1, wherein said step of growing a layer of a silicon compound includes growing a layer of silicon nitride of said first wafer.
Claim 9
Dependent Claim
53 words
The method according to claim 3, including the step of first diffusing a high conductivity layer into a surface of said first wafer prior to growing a layer of silicon compound over said surface, wherein said high conductivity layer determines the thickness of the active area of said diaphragm formed by said aperture.
Claim 10
Dependent Claim
18 words
The method according to claim 1, wherein the step of etching includes etching with a conductivity selective etch.
Claim 11
Dependent Claim
22 words
The method according to claim 1, wherein the step of diffusing includes diffusing P-type semiconductor material, including boron, into said second wafer.
Claim 12
Dependent Claim
97 words
the method according to claim 1, further including the steps of first growing a layer of silicon nitride on said second wafer, then growing a layer of silicon dioxide on said wafer, forming a resistive line pattern in said nitride layer, etching away said silicon dioxide to form a raised silicon nitride pattern regrowing a layer of silicon dioxide and then etching away said nitride to form a raised silicon pattern and then diffusing high conductivity semiconductor material into said second wafer according to said raised pattern prior to securing said raised pattern to said glass layer.
Claim 13
Dependent Claim
35 words
The method to claim 8 where the thickness of the active area is formed by employing a conductivity selective etch which will preferably attack the lower conductivity semiconductor without substantially etching the higher conductivity layer.
Claim 14
Dependent Claim
19 words
The method according to claim 2, wherein said resistor line pattern exhibits line widths between 0.1 to 1 mils.
Claim 15
Dependent Claim
15 words
The method according to claim 1, wherein said first and second wafers are monocrystalline semiconductors.
Claim 16
Dependent Claim
75 words
A semiconductor transducer structure comprising: a first carrier semiconductor wafer having a top composite surface including a first layer of an insulating silicon compound disposed on said surface with a layer of barosilicate glass disposed on said silicon compound, with a bottom surface having an aperture extending towards said top composite surface and defining an active area for deflection, a resistive pattern bonded to said glass layer and comprising single crystal high conductivity semiconductor material.
Claim 17
Dependent Claim
75 words
A semiconductor transducer structure comprising: a first carrier semiconductor wafer having a top composite surface including a first layer of an insulating silicon compound disposed on said surface with a layer of barosilicate glass disposed on said silicon compound, with a bottom surface having an aperture extending towards said top composite surface and defining an active area for deflection, a resistive pattern bonded to said glass layer and comprising single crystal high conductivity semiconductor material.
Claim 18
Dependent Claim
19 words
The semiconductor transducer structure according to claim 15, wherein said first layer of a silicon compound is silicon dioxide.
Claim 19
Dependent Claim
17 words
The semiconductor transducer structure according to claim 15, wherein said high conductivity material is P+ semiconductor material.
Claim 20
Dependent Claim
23 words
The semiconductor transducer according to claim 15, wherein said resistive pattern is bonded to said glass layer by means of an electrostatic bond.
Claim 21
Dependent Claim
17 words
The seimconductor transducer structure according to claim 15, further including a glass layer covering said resistive pattern.
Claim 22
Dependent Claim
18 words
The semiconductor transducer structure according to claim 15, further including a silicon dioxide layer covering said resistive pattern.
References Cited (Backward Citations)
US3819431A
Cited
US3951707A
Cited
US4016644A
Cited
US4204185A
Cited
US4523964A
Cited
US4481497A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-08 | 1990-12-08 | 1991-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-08 | 1994-12-08 | 1995-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-08 | 1998-12-08 | 1999-06-09 | $7700.00 | Window Closed / Lapsed |