US4682281A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data storage unit employing translation lookaside buffer pointer
Assignee: Fujitsu IT Holdings Inc
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Filing: 1983-08-30
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Granted: 1987-07-21
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Expires: 2003-08-30
Abstract
Abstract A data processing system includes virtual-addressed and real-addressed stores. Whenever an addressed location is not resident in the memory in which it is attempted to be accessed, the address is translated to the other address space. If a virtual address cannot access the desired location in the virtual memory the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real memory. Whenever a real address needs to access a virtual address in the virtual-addressed memory, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory. Virtual-to-real translation is carried out by storing the real addresses corresponding to a virtual address in a translation lookaside buffer. Entry to the translation lookaside buffer is gained by using a TLB pointer in a tag array which points to the TLB address which contains the desired real address. By storing a TLB pointer in the tag array rather than storing the full address, many bits are saved in the tag array.
Inventors
- 👤 Gary A. Woffinden
- 👤 Donald L. Hanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:02
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
257 words
A memory apparatus for a data processing system that generates logical addresses identifying requested data stored at locations in a mainstore addressed by system addresses; the apparatus comprising: register means, adapted for communication with the data processing system, for storing a requesting logical address, the logical address including a first field and a second field; translation lookaside buffer means, in communication with the register means, for storing translations to system addresses at translation lookaside buffer locations addressed by the first field of the requesting logical address; cache means, in communication with the register means and the mainstore, for storing data at cache location addressed by the second field of the requesting logical address, the cache location storing a version of data stored at a location in mainstore having a system address and storing a pointer pointing to a translation lookaside buffer location; means, in communication with the register means and the translation lookaside buffer means, for matching the requesting logical address with the translation at the translation lookaside buffer location addressed by the first field of requesting logical address to identify a valid translation to a system address; means, in communication with the register means and the cache means, for matching the pointer at the cache location addressed by the second field of the requesting logical address with the translation lookaside buffer location; and means, responsive to identification of a valid translation from the first matching means and a match of the pointer from the second matching means, for selecting the data out of the cache means.
Claim 2
Dependent Claim
257 words
A memory apparatus for a data processing system that generates logical addresses identifying requested data stored at locations in a mainstore addressed by system addresses; the apparatus comprising: register means, adapted for communication with the data processing system, for storing a requesting logical address, the logical address including a first field and a second field; translation lookaside buffer means, in communication with the register means, for storing translations to system addresses at translation lookaside buffer locations addressed by the first field of the requesting logical address; cache means, in communication with the register means and the mainstore, for storing data at cache location addressed by the second field of the requesting logical address, the cache location storing a version of data stored at a location in mainstore having a system address and storing a pointer pointing to a translation lookaside buffer location; means, in communication with the register means and the translation lookaside buffer means, for matching the requesting logical address with the translation at the translation lookaside buffer location addressed by the first field of requesting logical address to identify a valid translation to a system address; means, in communication with the register means and the cache means, for matching the pointer at the cache location addressed by the second field of the requesting logical address with the translation lookaside buffer location; and means, responsive to identification of a valid translation from the first matching means and a match of the pointer from the second matching means, for selecting the data out of the cache means.
Claim 3
Dependent Claim
55 words
The apparatus of claim 1, wherein the translations stored at translation lookaside buffer locations include a logical address and means for supplying a corresponding system address; and the means for matching the translation stored at the translation lookaside buffer location includes means for matching the logical address of the translation with the requesting logical address.
Claim 4
Dependent Claim
32 words
The apparatus of claim 2, wherein: the means for supplying a corresponding system address comprises means for storing at least a portion of the system address in the translation lookaside buffer location.
Claim 5
Dependent Claim
22 words
The apparatus of claim 1, wherein: the pointer stored at the cache location includes at least a subset of the first field.
Claim 6
Dependent Claim
24 words
The apparatus of claim 1, wherein the first and second fields of the requesting logical address include at least one address bit in common.
Claim 7
Dependent Claim
77 words
The apparatus of claim 1, wherein a subset of the logical addresses includes virtual addresses; and further including: virtual translator means, in communication with the register means and the translation lookaside buffer means, for translating virtual addresses in the register means to system addresses; and means, in communication with the translator means and responsive to the lack of identification of a valid translation, for signalling the virtual translator means to generate a translation to a system address.
Claim 8
Dependent Claim
77 words
The apparatus of claim 1, wherein a subset of the logical addresses includes real addresses; and further including: real translator means, in communication with the register means and the translation lookaside buffer means, for translating real addresses in the register means to system addresses; and means, in communication with the translator means and responsive to the lack of identification of a valid translation, for signalling the real translator means to generate a translation to a system address.
Claim 9
Dependent Claim
121 words
The apparatus of claim 1, wherein a first subset of the logical addresses includes virtual addresses and a second subset of the logical addresses includes real addresses; and further including: real translator means, in communication with the register means and the translation lookaside buffer means, for translating real addresses in the register means to system addresses; and virtual translator means, in communication with the register means and the translation lookaside buffer means, for translating virtual addresses in the register means to system addresses; and means, in communication with the real and virtual translator means and responsive to the lack of identification of a valid translation, for signalling the real and virtual translator means to generate a translation to a system address.
Claim 10
Dependent Claim
56 words
The apparatus of claim 1, further including: means, responsive to lack of identification of a valid translation, for replacing the translation at the translation lookaside buffer location with a new translation and for evicting data at cache locations that store a pointer to the translation lookaside buffer location for which the new translation is not valid.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-20 | 1991-01-19 | 1991-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-20 | 1995-01-19 | 1995-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-20 | 1999-01-19 | 1999-07-21 | $7700.00 | Window Closed / Lapsed |