US4685132A
Expired / Lapsed
US
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Bent sequence code generator
Assignee: Unisys Corp
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Filing: 1985-07-30
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Granted: 1987-08-04
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Expires: 2005-07-30
Abstract
Abstract A method and apparatus for generating a bent sequence code as a transform of an m-sequence code.
Inventors
- 👤 F. Avery Bishop
- 👤 Steven L. Bennett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 01:10
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L9/0668
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
138 words
A code generator comprising, register means for supplying an n length signal, transformation means for receiving said n length signal and transforming same into two n/2 length signals, permutation means for receiving one of said n/2 length signals and permuting same into a permutted signal, storage means for storing signals, said storage means connected to receive said permutted signal from said permutation means and the other one of said n/2 length signals from said transformation means, first summing means connected to the outputs of said storage means and said permutation means, sign inversion means selectively connected between said permutation means and said first summing means, second summing means connected to receive the output from said first summing means and a portion of said n length signal from said register means in order to produce a coded output signal.
Claim 2
Dependent Claim
138 words
A code generator comprising, register means for supplying an n length signal, transformation means for receiving said n length signal and transforming same into two n/2 length signals, permutation means for receiving one of said n/2 length signals and permuting same into a permutted signal, storage means for storing signals, said storage means connected to receive said permutted signal from said permutation means and the other one of said n/2 length signals from said transformation means, first summing means connected to the outputs of said storage means and said permutation means, sign inversion means selectively connected between said permutation means and said first summing means, second summing means connected to receive the output from said first summing means and a portion of said n length signal from said register means in order to produce a coded output signal.
Claim 3
Independent Claim
106 words
A method of producing a coded signal comprising, producing an n length signal, transforming said n length signal into a plurality of n/m length signals using any transform that will yield a bent sequence, permutting one of said plurality of n/m signals, supplying one of said n/m length signals and said permutted signal to a storage means to select the contents of a portion of said storage means, combining the selected contents of the storage means with the permutted n/m length signal to produce a combined signal, and combining a portion of said n length signal with the combined signal to produce the coded output signal.
Claim 4
Independent Claim
106 words
A method of producing a coded signal comprising, producing an n length signal, transforming said n length signal into a plurality of n/m length signals using any transform that will yield a bent sequence, permutting one of said plurality of n/m signals, supplying one of said n/m length signals and said permutted signal to a storage means to select the contents of a portion of said storage means, combining the selected contents of the storage means with the permutted n/m length signal to produce a combined signal, and combining a portion of said n length signal with the combined signal to produce the coded output signal.
Claim 5
Dependent Claim
23 words
The method of claim 2 including, selectively inverting the sign of the contents of said storage means prior to the first combining step.
Claim 6
Dependent Claim
16 words
The generator recited in claim 1 wherein, said register means includes a plurality of bistable stages.
Claim 7
Dependent Claim
13 words
The generator recited in claim 4 wherein, said bistable stages include flip-flop means.
Claim 8
Dependent Claim
49 words
The generator recited in claim 1 wherein, said transformation means includes a plurality of devices each connected to receive a portion of said n length signal from said register means and operative to produce a portion of each said n/2 signal as a function of the signals supplied thereto.
Claim 9
Dependent Claim
31 words
The generator recited in claim 6 wherein, said devices each comprise a parity checker circuit which produces an output signal representative of the input signals supplied thereto by said register means.
Claim 10
Dependent Claim
35 words
The generator recited in claim 1 wherein, said permutation means includes a plurality of circuit devices which produce different output signals in response to prescribed input signals in accordance with a control signal supplied thereto.
Claim 11
Dependent Claim
18 words
The generator recited in claim 8 including, control means for supplying said control signal to said circuit devices.
Claim 12
Dependent Claim
20 words
The generator recited in claim 1 wherein, said storage means comprises a memory device which stores a Hadamard matrix function.
Claim 13
Dependent Claim
13 words
The generator recited in claim 10 wherein, said storage means comprises a ROM.
Claim 14
Dependent Claim
16 words
The generator recited in claim 1 wherein, said first summing means comprises a modulo 2 adder.
Claim 15
Dependent Claim
16 words
The generator recited in claim 12 wherein, said second summing means comprises a modulo 2 adder.
Claim 16
Dependent Claim
23 words
The generator recited in claim 1 wherein, said second summing means is connected to receive the last bit of said m length signal.
Claim 17
Dependent Claim
22 words
The generator recited in claim 13 wherein, each of said first and second summing means comprise at least one Exclusive OR gate.
Claim 18
Dependent Claim
57 words
The generator recited in claim 1 wherein, said storage means includes rows and columns of storage elements, and said permuted signal from said permuation means is used to address the columns of said storage means, said other one of said n/2 length signals from said transformation means is used to address the rows of said storage means.
Claim 19
Dependent Claim
45 words
The generator recited in claim 1 including, code sequence signal source means, and third summing means connected to receive the coded output signal from said second summing means and code sequence signals from said code sequence signal means and to produce a composite pseudo-noise signal.
Claim 20
Dependent Claim
33 words
The generator recited in claim 5 including, a plurality of Exclusive-OR gates connected to receive signals from different flip-flop means and to supply signals to the inputs of flip-flop means in adjacent stages.
Claim 21
Dependent Claim
42 words
The generator recited in claim 18 including, NOR gate means connected to receive signals from each of the flip-flop means in said register means and to supply a signal of the flip-flop means in the first bistable stage in said register means.
Claim 22
Dependent Claim
22 words
The generator recited in claim 18 wherein, each of the flip-flop means produces a signal which is supplied to the transformation means.
Claim 23
Dependent Claim
39 words
The generator recited in claim 7 wherein, a first plurality of parity checker circuits are connected to supply said permutation means, and a second plurality of said parity checker circuits is connected to supply signals to said storage means.
Claim 24
Dependent Claim
13 words
The generator recited in claim 8 wherein, said circuit devices comprise multiplexer means.
Claim 25
Dependent Claim
58 words
The generator recited in claim 22 including, converter mean for converting the signals from said transformation means into a prescribed number signal representative of the value of the signals from said transformation means and connected to supply said number signal to said multiplexer means for selective transfer therethrough in response to the control signals supplied to said multiplexers.
Claim 26
Dependent Claim
38 words
The generator recited in claim 23 including, decoder means connected to receive signals from said multiplexer means and to convert these signals to output signals representative of the signals supplied to said converter means by said transformation means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-03 | 1991-02-02 | 1991-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-03 | 1995-02-02 | 1995-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-03 | 1999-02-02 | 1999-08-04 | $7700.00 | Window Closed / Lapsed |