Method of forming vertically integrated current source

Claim 1

A method for forming a semiconductor device, comprising: providing a silicon substrate of a first conductivity type; forming a first buried region of a second conductivity type in the silicon substrate; forming a trench in the silicon substrate extending through the first buried region, the trench having sidewalls and a bottom, the bottom extending into the substrate and below the first buried region; forming an insulating layer on the sidewalls of the trench; forming a second buried region of the second conductivity type in the silicon substrate at the bottom of the trench; forming a conductive layer over the bottom of the trench contacting said second buried region and over the insulating layer covering the sidewalls of the trench to form a gate region on the sidewalls which is conductively connected with the second buried region; the area in the silicon substrate adjacent the trench and between the first and second buried regions comprising a channel region; and forming a first interconnect to the conductive layer and forming a second interconnect to the first buried region, the first and second interconnects operable to be interfaced with external circuitry.

Claim 2

A method for forming a semiconductor device, comprising: providing a silicon substrate of a first conductivity type; forming a first buried region of a second conductivity type in the silicon substrate; forming a trench in the silicon substrate extending through the first buried region, the trench having sidewalls and a bottom, the bottom extending into the substrate and below the first buried region; forming an insulating layer on the sidewalls of the trench; forming a second buried region of the second conductivity type in the silicon substrate at the bottom of the trench; forming a conductive layer over the bottom of the trench contacting said second buried region and over the insulating layer covering the sidewalls of the trench to form a gate region on the sidewalls which is conductively connected with the second buried region; the area in the silicon substrate adjacent the trench and between the first and second buried regions comprising a channel region; and forming a first interconnect to the conductive layer and forming a second interconnect to the first buried region, the first and second interconnects operable to be interfaced with external circuitry.

Claim 9

A method for forming a semiconductor current source, comprising: defining a moat region in a silicon substrate of a first conductivity type; ion implanting a dopant of a second conductivity type in the moat region to define a first buried region; depositing a layer of protective oxide over the substrate; anisotropically etching a trench through said first buried region, the trench having sidewalls and a bottom portion, the bottom portion disposed below the first buried region a predetermined distance; ion implanting a dopant of the second conductivity type in the bottom of the trench to define a second buried region, the portion of the silicon substrate between the first buried region and the second buried region adjacent the sidewalls of the trench forming a channel region; oxidizing the exposed silicon surfaces on the sidewalls of the trench and in the bottom of the trench to form a gate oxide of a predetermined thickness; removing the portion of the gate oxide covering the bottom portion of the trench; depositing a conformal layer of polycrystalline silicon over the substrate to cover the gate oxide in the trench and the second buried region and being in conductive contact with the second buried region; patterning and etching the polycrystalline silicon layer such that polycrystalline silicon remains over the gate oxide layer in the trench and the second buried region and extends upward above the substrate to define a first terminal for the current source; and forming a metal contact to the first buried region to define a second terminal for the current source.

Claim 10

A method for forming a semiconductor current source, comprising: defining a moat region in a silicon substrate of a first conductivity type; ion implanting a dopant of a second conductivity type in the moat region to define a first buried region; depositing a layer of protective oxide over the substrate; anisotropically etching a trench through said first buried region, the trench having sidewalls and a bottom portion, the bottom portion disposed below the first buried region a predetermined distance; ion implanting a dopant of the second conductivity type in the bottom of the trench to define a second buried region, the portion of the silicon substrate between the first buried region and the second buried region adjacent the sidewalls of the trench forming a channel region; oxidizing the exposed silicon surfaces on the sidewalls of the trench and in the bottom of the trench to form a gate oxide of a predetermined thickness; removing the portion of the gate oxide covering the bottom portion of the trench; depositing a conformal layer of polycrystalline silicon over the substrate to cover the gate oxide in the trench and the second buried region and being in conductive contact with the second buried region; patterning and etching the polycrystalline silicon layer such that polycrystalline silicon remains over the gate oxide layer in the trench and the second buried region and extends upward above the substrate to define a first terminal for the current source; and forming a metal contact to the first buried region to define a second terminal for the current source.