Semiconductor device having high breakdown voltage

Claim 2

A semiconductor device having a high breakdown voltage, comprising: a semiconductor substrate having between opposite principal surfaces thereof at least three semiconductor layers which are adjacent to each other with alternately different conductivity types to form pn junctions therebetween, one of the outermost layers of said at least three semiconductor layers being on the side of one of said opposite principal surfaces of said semiconductor substrate, the other outermost semiconductor layer being on the side of the other principal surface, at least predetermined ones of said pn junctions having end portions exposed to said one principal surface of said semiconductor substrate; a first main electrode provided on said one principal surface in low-resistance contact with one outermost semiconductor layer; a second main electrode provided on said other principal surface in low-resistance contact with said other outermost semiconductor layer; a control electrode provided on said one principal surface in low-resistance contact with an intermediate layer of said at least three semiconductor layers adjacent to said one outermost semiconductor layer; an additional electrode provided on said one principal surface in low-resistance contact therewith, said additional electrode having a potential substantially equal to said other outermost semiconductor layer which is in low-resistance contact with said second main electrode; a surface-passivation insulating film provided on said one principal surface to cover the exposed end portions of said predetermined ones of said pn junctions for passivation thereof; and a resistive material sheet provided on said surface-passivation insulating film, wherein said resistive material sheet contacts with said first main electrode which is kept in low-resistance contact with said one outermost semiconductor layer, and further wherein said resistive material sheet contacts said additional electrode which has a potential equal to said other outermost semiconductor layer.

Claim 3

A semiconductor device according to claim 1, wherein said resistive material sheet is disposed on the exposed end portions of said predetermined ones of said junctions through said surface-passivation insulating film.

Claim 4

A semiconductor device according to claim 1, wherein said resistive material sheet includes a semi-insulating, oxygen-containing amorphous silicon layer or a semi-insulating, polycrystalline semiconductor layer.

Claim 5

A semiconductor device according to claim 1, wherein said intermediate semiconductor layer adjacent to said one outermost semiconductor layer includes a highly-doped layer in said one principal surface, said control electrode being kept in low-resistance contact with said highly-doped layer.

Claim 6

A semiconductor device according to claim 1, wherein said first main electrode extends across the exposed end portions of said predetermined ones of said pn junctions.

Claim 7

A semiconductor device according to claim 1, wherein said at least three semiconductor layers are all exposed to said one principal surface.

Claim 8

A semiconductor device according to claim 1, wherein said semiconductor substrate has a four-layer structure of pnpn.

Claim 9

A semiconductor device according to claim 1, wherein said semiconductor substrate has a four-layer structure of pnpn, said second main electrode being also kept in low-resistance contact with an intermediate semiconductor layer adjacent to said other outermost semiconductor layer.

Claim 10

A semiconductor device according to claim 1, wherein said semiconductor substrate has a three-layer structure in which said one outermost semiconductor layer and said intermediate semiconductor layer are exposed to said one principal surface and said other outermost semiconductor layer is exposed to both said one and the other principal surfaces, and wherein all of said pn junctions have the end portions exposed to said one principal surface, said additional electrode being kept in low-resistance contact with that portion of said other outermost semiconductor layer which is exposed to said one principal surface.

Claim 11

A semiconductor device according to claim 9, wherein said intermediate semiconductor layer has an impurity concentration which is highest at said one principal surface and decreases with increased depth from said one principal surface.

Claim 12

A semiconductor device according to claim 9, wherein said intermediate semiconductor layer includes a higher-doped region in said one principal surface, said control electrode being kept in low-resistance contact with said highly-doped region.

Claim 13

A semiconductor device according to claim 9, wherein said first main electrode extends toward said additional electrode on said resistive material sheet beyond the exposed end portion of the pn junction formed between said intermediate semiconductor layer and said other outermost semiconductor layer.

Claim 14

A semiconductor device according to claim 1, wherein said semiconductor substrate has a four-layer structure in which said one outermost semiconductor layer, said intermediate semiconductor layer adjacent to said one outermost semiconductor layer, and an intermediate semiconductor layer adjacent to said other outermost semiconductor layer are exposed to said one principal surface and said other outermost semiconductor layer is exposed to both said one and said other principal surfaces, and wherein all of said pn junctions have the end portions exposed to said one principal surface, said additional electrode being kept in low-resistance contact with that portion of said other outermost semiconductor layer which is exposed to said one principal surface.

Claim 15

A semiconductor device according to claim 13, wherein said intermediate semiconductor layer adjacent to said one outermost semiconductor layer includes a highly-doped region in said one principal surface, said control electrode being kept in low-resistance contact with said highly-doped region.

Claim 16

A semiconductor device according to claim 13, wherein said first main electrode extends toward said additional electrode on said resistive material sheet beyond the exposed end portion of the pn junction formed between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer.

Claim 17

A semiconductor device according to claim 13, wherein said additional electrode extends toward said first main electrode on said resistive material sheet beyond the exposed end portion of the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer.

Claim 18

A semiconductor device according to claim 13, wherein said intermediate layer adjacent to said other outermost semiconductor layer includes a highly-doped region in said one principal surface between the exposed end portion of the pn junction formed between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer and the exposed end portion of the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer, said resistive material sheet contacting with said highly-doped region through an opening which is provided in said surface-passivation insulating film.

Claim 19

A semiconductor device according to claim 13, wherein said resistive material sheet includes a first resistive material sheet contacting with said first main electrode and a second resistive material sheet contacting with said additional electrode, said intermediate semiconductor laye includes a highly-doped region in said one principal surface between the exposed end portion of the pn junction formed between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer and the exposed end portion of the pn junction formed between said other semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer, and a channel cut electrode is kept in low-resistance contact with said highly-doped region through an opening provided in said surface-passivation insulating film, said channel cut electrode contacting with both said first and second resistive material sheets.

Claim 20

A semiconductor device according to claim 1, wherein said semiconductor substrate has a four-layer structure in which said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said one outermost semiconductor layer are exposed to said one principal surface, an intermediate semiconductor layer adjacent to said other outermost semiconductor layer is exposed to both said one and said other principal surfaces, and said other outermost semiconductor layer is exposed to said other principal surface, and wherein all of said pn junction excepting the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer have the end portions exposed to said one principal surface, said second main electrode being also kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said other principal surface, said additional electrode being kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said one principal surface.

Claim 21

A semiconductor device according to claim 19, wherein said intermediate semiconductor layer adjacent to said one outermost semiconductor layer includes a highly-doped region in said principal surface, said control electrode being kept in low-resistance contact with said highly-doped region.

Claim 22

A semiconductor device according to claim 19, wherein said first main electrode extends toward said additional electrode on said resistive material sheet beyond the exposed end portion of the pn junction formed between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer.

Claim 23

A semiconductor device according to claim 1, wherein said semiconductor substrate has a five-layer structure in which said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said one outermost semiconductor layer are exposed to said one principal surface, an intermediate semiconductor layer adjacent to said other outermost semiconductor layer is exposed to both said one and said other principal surfaces, an intermediate semiconductor layer existing between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer is exposed to said one principal surface, and said other outermost semiconductor layer is exposed to said other principal surface, and wherein all of said pn junctions excepting the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer have the end portions exposed to said one principal surface, said second main electrode being also kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said other principal surface, said additional electrode being kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said one principal surface.

Claim 24

A semiconductor device according to claim 22, wherein said intermediate semiconductor layer adjacent to said one outermost semiconductor layer includes a highly-doped region in said principal surface, said control electrode being kept in low-resistance contact with said highly-doped region.

Claim 25

A semiconductor device according to claim 22, wherein said first main electrode extends toward said additional electrode on said resistive material sheet beyond the exposed end portion of the pn junction formed between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer existing between said intermediate semiconductor layer adjacent to said one outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer.

Claim 26

A semiconductor device according to claim 22, wherein said first main electrode is also kept in low-resistance contact with said intermediate semiconductor layer adjacent to said one outermost semiconductor layer.

Claim 27

A semiconductor device having a high breakdown voltage, comprising: a semiconductor substrate having upper and lower principal surfaces, said substrate including at least three semiconductor layers which are adjacent to each other with alternately different conductivity types to form pn junctions therebetween, one of the outermost layers of said at least three semiconductor layers and an intermediate layer of said at least three semiconductor layers adjacent to said one outermost semiconductor layer being exposed to said upper principal surface, the other outermost semiconductor layer being exposed to both said upper and lower principal surfaces, said pn junctions having end portions exposed to said upper principal surface; upper and lower main electrodes provided on said upper and lower principal surfaces in low-resistance contact with said one and other outermost semiconductor layers, respectively; a control electrode provided on said upper principal surface in low-resistance contact with said intermediate semiconductor layer adjacent to said one outermost semiconductor layer; an additional electrode provided on said upper principal surface in low-resistance contact with that portion of said other outermost semiconductor layer which is exposed to said upper principal surface; a surface-passivation insulating film provided on said upper principal surface to cover the exposed end portions of said pn junctions for passivation thereof; and a resistive material sheet provided on said surface-passivation insulating film in contact with said upper main electrode and said additional electrode.

Claim 28

A semiconductor device having a high breakdown voltage, comprising: a semiconductor substrate having upper and lower principal surfaces, said substrate including at least three semiconductor layers which are adjacent to each other with alternately different conductivity types to form pn junctions therebetween, one of the outermost layers of said at least three semiconductor layers and an intermediate layer of said at least three semiconductor layers adjacent to said one outermost semiconductor layer being exposed to said upper principal surface, the other outermost semiconductor layer being exposed to both said upper and lower principal surfaces, said pn junctions having end portions exposed to said upper principal surface; upper and lower main electrodes provided on said upper and lower principal surfaces in low-resistance contact with said one and other outermost semiconductor layers, respectively; a control electrode provided on said upper principal surface in low-resistance contact with said intermediate semiconductor layer adjacent to said one outermost semiconductor layer; an additional electrode provided on said upper principal surface in low-resistance contact with that portion of said other outermost semiconductor layer which is exposed to said upper principal surface; a surface-passivation insulating film provided on said upper principal surface to cover the exposed end portions of said pn junctions for passivation thereof; and a resistive material sheet provided on said surface-passivation insulating film in contact with said upper main electrode and said additional electrode.

Claim 29

A semiconductor device having a high breakdown voltage, comprising: a semiconductor substrate having upper and lower principal surfaces, said substrate including at least four semiconductor layers which are adjacent to each other with alternately different conductivity types to form pn junctions therebetween, one of the outermost layers of said at least four semiconductor layers and an intermediate layer of said at least four semiconductor layers adjacent to said one outermost semiconductor layer being exposed to said upper principal surface, an intermediate layer of said at least four semiconductor layers adjacent to the other outermost semiconductor layer being exposed to both said upper and lower principal surfaces, said other outermost semiconductor layer being exposed to said lower principal surface, end portions of all of said pn junctions except the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer being exposed to said upper principal surface; upper and lower main electrodes provided on said upper and lower principal surfaces in low-resistance contact with said one and other outermost semiconductor layers, respectively, said lower main electrode being also kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said lower principal surface; a control electrode provided on said upper principal surface in low-resistance contact with said intermediate semiconductor layer adjacent to said one outermost semiconductor layer; an additional electrode provided on said upper principal surface in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said upper principal surface; a surface-passivation insulating film provided on said upper principal surface to cover the exposed end portions of said pn junctions exposed to said upper prinipal surface for passivation thereof; and a resistive material sheet provided on said surface-passivation insulating film in contact with said upper main electrode and said additional electrode.

Claim 30

A semiconductor device having a high breakdown voltage, comprising: a semiconductor substrate having upper and lower principal surfaces, said substrate including at least four semiconductor layers which are adjacent to each other with alternately different conductivity types to form pn junctions therebetween, one of the outermost layers of said at least four semiconductor layers and an intermediate layer of said at least four semiconductor layers adjacent to said one outermost semiconductor layer being exposed to said upper principal surface, an intermediate layer of said at least four semiconductor layers adjacent to the other outermost semiconductor layer being exposed to both said upper and lower principal surfaces, said other outermost semiconductor layer being exposed to said lower principal surface, end portions of all of said pn junctions except the pn junction formed between said other outermost semiconductor layer and said intermediate semiconductor layer adjacent to said other outermost semiconductor layer being exposed to said upper principal surface; upper and lower main electrodes provided on said upper and lower principal surfaces in low-resistance contact with said one and other outermost semiconductor layers, respectively, said lower main electrode being also kept in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said lower principal surface; a control electrode provided on said upper principal surface in low-resistance contact with said intermediate semiconductor layer adjacent to said one outermost semiconductor layer; an additional electrode provided on said upper principal surface in low-resistance contact with that portion of said intermediate semiconductor layer adjacent to said other outermost semiconductor layer which is exposed to said upper principal surface; a surface-passivation insulating film provided on said upper principal surface to cover the exposed end portions of said pn junctions exposed to said upper prinipal surface for passivation thereof; and a resistive material sheet provided on said surface-passivation insulating film in contact with said upper main electrode and said additional electrode.