US4695750A
Expired / Lapsed
US
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Voltage level converting circuit
Assignee: Toshiba Corp
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Filing: 1985-08-28
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Granted: 1987-09-22
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Expires: 2005-08-28
Abstract
Abstract A voltage level converting circuit includes first and second potential terminals between which a power source voltage is applied, first and second terminals for receiving an input signal and an inverted input signal, a differential amplifier including npn transistors whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier. The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals by way of a constant current source, and includes a MOS transistor whose conduction state is controlled by the output voltage of the differential amplifier.
Inventors
- 👤 Hiroyuki Hara
- 👤 Michinori Nakamura
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527; H03K19/01; H03K19/017; H03K19/01707
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
408 words
A voltage level converting circuit for an input interface to a TTL circuit, comprising: first and second potential terminals between which a power source voltage is applied; first and second input terminals coupled for respectively receiving an input signal and an inverted input signal from an ECL circuit; a differential amplifier for detecting a voltage difference between said input and said inverted input signals, including: first and second bipolar transistors each having a base, collector, and emitter, with the bases respectively connected to the first and second input terminals, and with the collector of the first bipolar transistor connected only to the first potential terminal, a first constant current source connected to the emitters of the first and second bipolar transistors and connected to the second potential terminal, a first MOS transistor, with a source connected to the first potential terminal, and with the collector of the second bipolar transistor connected to a drain and a gate of the MOS transistor, for providing a current path from the first potential terminal to the collector of the second bipolar transistor at times when the second bipolar transistor is turned on, wherein the first and second bipolar transistors are respectively turned on and off at times when the input signal is at a high voltage, and the first and second bipolar transistors are respectively turned off and on at times when the input signal is at a low voltage; and an output circuit for generating an output logic voltage in accordance with the detected voltage difference, including: a second MOS transistor, with a source connected to the first potential terminal, with the collector of the second bipolar transistor connected only to a gate of the second MOS transistor and to the drain and gate of the first MOS transistor, and a drain, a second constant current source connected to the drain of the second MOS transistor and to the second potential terminal, and an output terminal at which the output logic voltage is generated connected to the drain of the second MOS transistor, wherein a current path is provided from the first potential terminal to the output terminal and generates the output logic voltage at a high level at times when the second bipolar transistor is turned on, and a current path is not provided from the first potential terminal and generates the output logic voltage at a low level at times when the second bipolar transistor is turned off.
Claim 2
Dependent Claim
408 words
A voltage level converting circuit for an input interface to a TTL circuit, comprising: first and second potential terminals between which a power source voltage is applied; first and second input terminals coupled for respectively receiving an input signal and an inverted input signal from an ECL circuit; a differential amplifier for detecting a voltage difference between said input and said inverted input signals, including: first and second bipolar transistors each having a base, collector, and emitter, with the bases respectively connected to the first and second input terminals, and with the collector of the first bipolar transistor connected only to the first potential terminal, a first constant current source connected to the emitters of the first and second bipolar transistors and connected to the second potential terminal, a first MOS transistor, with a source connected to the first potential terminal, and with the collector of the second bipolar transistor connected to a drain and a gate of the MOS transistor, for providing a current path from the first potential terminal to the collector of the second bipolar transistor at times when the second bipolar transistor is turned on, wherein the first and second bipolar transistors are respectively turned on and off at times when the input signal is at a high voltage, and the first and second bipolar transistors are respectively turned off and on at times when the input signal is at a low voltage; and an output circuit for generating an output logic voltage in accordance with the detected voltage difference, including: a second MOS transistor, with a source connected to the first potential terminal, with the collector of the second bipolar transistor connected only to a gate of the second MOS transistor and to the drain and gate of the first MOS transistor, and a drain, a second constant current source connected to the drain of the second MOS transistor and to the second potential terminal, and an output terminal at which the output logic voltage is generated connected to the drain of the second MOS transistor, wherein a current path is provided from the first potential terminal to the output terminal and generates the output logic voltage at a high level at times when the second bipolar transistor is turned on, and a current path is not provided from the first potential terminal and generates the output logic voltage at a low level at times when the second bipolar transistor is turned off.
Claim 3
Dependent Claim
30 words
A voltage level converting circuit according to claim 1, wherein said second constant current source includes a third MOS transistor of a conductivity type opposite to said second MOS transistor.
Claim 4
Dependent Claim
64 words
A voltage level converting circuit according to claim 2, wherein the third MOS transistor has a current path connected between the drain of said second MOS transistor and the second potential terminal, and has a gate supplied with a predetermined bias voltage required to keep the amount of current flowing through the third MOS transistor smaller than that flowing through the second MOS transistor.
Claim 5
Dependent Claim
31 words
A voltage level converting circuit according to claim 2, wherein the first and second bipolar transistors are of an npn type, and the first MOS transistor is of a p-channel type.
Claim 6
Dependent Claim
24 words
A voltage level converting circuit according to claim 4, wherein the second and third MOS transistors are of the p-channel and n-channel types, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-21 | 1991-03-23 | 1991-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-21 | 1995-03-23 | 1995-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-21 | 1999-03-23 | 1999-09-22 | $7700.00 | Window Closed / Lapsed |