Process for isolation using self-aligned diffusion process

Claim 2

In a process for fabricating semi-oxide insulated devices, which includes providing a substrate, forming patterned regions of a first conductivity type in a major surface of said substrate, forming an epitaxial layer on said substrate over said major surface, forming a patterned mask layer on said epitaxial layer so as to define openings therethrough to expose portions of said epitaxial layer, removing said exposed portions of said epitaxial layer to define mesa structures which overlie said patterned regions of said first conductivity type, forming regions of a second conductivity type in said substrate between said patterned regions, forming a field oxide between said mesa structures, and forming devices on said mesa structures, wherein said devices are isolated from each other by said regions of said second conductivity type, the improvement which comprises: (a) employing as said patterned mask a mask consisting essentially of a material selected from the group consisting of (1) a multilayer structure comprising at least two each of alternating layers of silicon dioxide and silicon nitride, (2) silicon nitride and (3) metal; (b) removing said exposed portions of said epitaxial layer by a partially anisotropic etchant to undercut portions of said patterned mask, form said mesa structures having side walls, and expose portions of said substrate; (c) forming an oxide layer on said side walls of said mesa structure and on said exposed portions of said substrate; (d) removing said oxide layer lying under said openings in said patterned mask to expose corresponding regions of said substrate, said corresponding regions lying between said patterned regions; and (e) forming said regions of said second conductivity in said corresponding regions through openings in said oxide layer.

Claim 3

The process of claim 1 wherein said substrate comprises silicon.

Claim 4

The process of claim 1 wherein said patterned regions of said first conductivity type are doped with an N-type dopant.

Claim 5

The process of claim 1 wherein said patterned mask comprises a first layer of a buffer oxide, a second layer of silicon nitride, a third layer of undoped silicon dioxide and a fourth layer of silicon nitride.

Claim 6

The process of claim 4 wherein said first layer is formed to a thickness of about 300 to 500 Å, said second layer is formed to a thickness of about 1000 to 1200 Å, said third layer is formed to a thickness of about 1500 to 2000 Å and said fourth layer is formed to a thickness of about 700 to 1000 Å.

Claim 7

The process of claim 5 wherein said first layer is formed by a thermal process; said second and fourth layers are formed by a chemical vapor deposition process and said third layer is formed by an oxidation deposition process.

Claim 8

The process of claim 1 wherein said openings in said mask are formed by etching through portions of said mask with a plasma.

Claim 9

The process of claim 1 wherein said epitaxial layer comprises silicon and is formed with its (100) planes parallel to said major surface of said substrate.

Claim 10

The process of claim 8 wherein said epitaxial layer is etched by said anisotropic etchant which etches least along the (111) plane.

Claim 11

The process of claim 1 wherein said oxide is formed on the side walls of said mesa structures and on said exposed portions of said substrate by a dry thermal process.

Claim 12

The process of claim 10 wherein said oxide is formed to a thickness of about 1000 to 1500 Å.

Claim 13

The process of claim 10 wherein said exposed portions of said epitaxial layer are removed by said at least partially anisotropic etchant to the extent that any epitaxial layer remaining over said substrate is completely converted to oxide by said dry thermal process.

Claim 14

The process of claim 1 wherein that portion of said oxide layer underlying said openings is removed by reactive ion etching, employing fluoride ions.

Claim 15

The process of claim 1 wherein said regions of said second conductivity are doped with a P-type dopant.

Claim 16

The process of claim 14 wherein said P-type dopant consists essentially of boron.

Claim 17

The process of claim 15 wherein said boron is introduced by a diffusion process.

Claim 18

The process of claim 14 wherein said substrate carrying said mesa structures is annealed to remove damage caused by introducing said dopant.

Claim 19

The process of claim 1 wherein said mask layer comprises a thick silicon nitride.

Claim 20

The process of claim 1 wherein said mask layer comprises a metal mask.

Claim 21

In a process for fabricating semi-oxide insulated devices, which includes providing a silicon substrate, forming N-type doped patterned regions in a major surface of said substrate, forming an epitaxial silicon layer on said substrate over said major surface, forming a patterned mask layer on said epitaxial layer to expose portions of said epitaxial layer, removing said exposed portions of said epitaxial layer to define mesa structures which overlie said patterned regions, forming P + -type doped regions in said substrate between said patterned regions, forming a field oxide between said mesa structures, and forming devices on said mesa structures, wherein said devices are isolated from each other by said P + -type regions, the improvement which comprises: (a) forming said epitaxial layer having a crystallographic orientation of its (100) planes parallel to said major surface of said substrate; (b) forming said patterned mask so as to define openings therethrough, said patterned mask comprising a first layer of a buffer silicon dioxide, a second layer of silicon nitride, a third layer of undoped silicon dioxide and a fourth layer of silicon nitride; (c) removing said exposed portions of said epitaxial layer by a partially anisotropic etchant which etches least along the (111) planes of said epitaxial layer to undercut portions of said patterned mask, form said mesa structures having side walls, and expose portions of said substrate; (d) forming a silicon dioxide layer on said side walls of said mesa structures and on said exposed portions of said substrate; (e) removing said silicon dioxide layer lying under said openings in said patterned mask by reactive ion etching to expose corresponding regions of said substrate, said corresponding regions lying between said patterned regions; and (f) forming said P + -type regions in said corresponding regions by introducing a P-type dopant through openings in said silicon dioxide.

Claim 22

In a process for fabricating semi-oxide insulated devices, which includes providing a silicon substrate, forming N-type doped patterned regions in a major surface of said substrate, forming an epitaxial silicon layer on said substrate over said major surface, forming a patterned mask layer on said epitaxial layer to expose portions of said epitaxial layer, removing said exposed portions of said epitaxial layer to define mesa structures which overlie said patterned regions, forming P + -type doped regions in said substrate between said patterned regions, forming a field oxide between said mesa structures, and forming devices on said mesa structures, wherein said devices are isolated from each other by said P + -type regions, the improvement which comprises: (a) forming said epitaxial layer having a crystallographic orientation of its (100) planes parallel to said major surface of said substrate; (b) forming said patterned mask so as to define openings therethrough, said patterned mask comprising a first layer of a buffer silicon dioxide, a second layer of silicon nitride, a third layer of undoped silicon dioxide and a fourth layer of silicon nitride; (c) removing said exposed portions of said epitaxial layer by a partially anisotropic etchant which etches least along the (111) planes of said epitaxial layer to undercut portions of said patterned mask, form said mesa structures having side walls, and expose portions of said substrate; (d) forming a silicon dioxide layer on said side walls of said mesa structures and on said exposed portions of said substrate; (e) removing said silicon dioxide layer lying under said openings in said patterned mask by reactive ion etching to expose corresponding regions of said substrate, said corresponding regions lying between said patterned regions; and (f) forming said P + -type regions in said corresponding regions by introducing a P-type dopant through openings in said silicon dioxide.

Claim 23

The process of claim 20 wherein said first layer is formed to a thickness of about 300 to 500 Å, said second layer is formed to a thickness of about 1000 to 1200 Å, said third layer is formed to a thickness of about 1500 to 2000 Å and said fourth layer is formed to a thickness of about 700 to 1000 Å.

Claim 24

The process of claim 21 wherein said first layer is formed by a thermal process; said second and fourth layers are formed by a chemical vapor deposition process and said third layer is formed by a low temperature Silox process.

Claim 25

The process of claim 20 wherein said openings in said mask are formed by etching said mask with a plasma.

Claim 26

The process of claim 20 wherein said silicon dioxide is formed on the side walls of said mesa structures and on said exposed portions of said substrate by a dry thermal process.

Claim 27

The process of claim 24 wherein said oxide is formed to a thickness of about 1000 to 1500 Å.

Claim 28

The process of claim 20 wherein said P-type dopant consists essentially of boron.

Claim 29

The process of claim 26 wherein said boron is introduced by a diffusion process.

Claim 30

The process of claim 20 wherein said substrate carrying said mesa structures is annealed to remove damage caused by introducing said dopant.

Claim 31

A process for fabricating semiconductor devices on a plurality of mesa structures supported on a silicon substrate, including: (a) forming N-type doped patterned regions in a major surface of said substrate; (b) forming an epitaxial silicon layer on said substrate over said major surface, said epitaxial silicon layer having a crystallographic orientation of its (100) planes parallel to said major surface; (c) forming a patterned mask layer on said epitaxial layer, said patterned mask comprising a first layer of silicon dioxide, a second layer of silicon nitride, a third layer of undoped silicon dioxide and a fourth layer of silicon nitride; (d) forming openings in said patterned mask layer to expose portions of said epitaxial layer; (e) removing said exposed portions of said epitaxial layer to define mesa structures which overlie said patterned regions, said exposed portions being removed by use of an anisotropic etchant which etches least along the (111) planes of said epitaxial layer to undercut portions of said patterned mask; (f) forming a silicon dioxide layer on side walls of said mesa structures and on exposed portions of said substrate; (g) removing those portions of said silicon dioxide layer lying under said openings in said patterned mask to expose corresponding regions of said substrate, said corresponding regions lying between said patterned regions; (h) diffusing a P-type dopant to form P + -type doped regions in said substrate between said patterned regions; (i) annealing said substrate carrying said mesa structures to remove damage caused by introducing dopant to form said doped regions; (j) forming a field oxide between said mesa structures; and (k) forming devices on said mesa structures, wherein said devices are isolated from each other by said P + regions.

Claim 32

A process for fabricating semiconductor devices on a plurality of mesa structures supported on a silicon substrate, including: (a) forming N-type doped patterned regions in a major surface of said substrate; (b) forming an epitaxial silicon layer on said substrate over said major surface, said epitaxial silicon layer having a crystallographic orientation of its (100) planes parallel to said major surface; (c) forming a patterned mask layer on said epitaxial layer, said patterned mask comprising a first layer of silicon dioxide, a second layer of silicon nitride, a third layer of undoped silicon dioxide and a fourth layer of silicon nitride; (d) forming openings in said patterned mask layer to expose portions of said epitaxial layer; (e) removing said exposed portions of said epitaxial layer to define mesa structures which overlie said patterned regions, said exposed portions being removed by use of an anisotropic etchant which etches least along the (111) planes of said epitaxial layer to undercut portions of said patterned mask; (f) forming a silicon dioxide layer on side walls of said mesa structures and on exposed portions of said substrate; (g) removing those portions of said silicon dioxide layer lying under said openings in said patterned mask to expose corresponding regions of said substrate, said corresponding regions lying between said patterned regions; (h) diffusing a P-type dopant to form P + -type doped regions in said substrate between said patterned regions; (i) annealing said substrate carrying said mesa structures to remove damage caused by introducing dopant to form said doped regions; (j) forming a field oxide between said mesa structures; and (k) forming devices on said mesa structures, wherein said devices are isolated from each other by said P + regions.

Claim 33

The process of claim 29 wherein said first layer is formed to a thickness of about 300 to 500 Å, said second layer is formed to a thickness of about 1000 to 1200 Å, said third layer is formed to a thickness of about 1500 to 2000 Å and said fourth layer is formed to a thickness of about 700 to 1000 Å, with said third layer being at least about 200 Å thicker than said silicon dioxide layer formed on said side walls of said mesa.

Claim 34

The process of claim 29 wherein said openings in said silicon dioxide layer formed on said substrate are etched by reactive ion etching.

Claim 35

The process of claim 31 wherein said reactive ion consists essentially of fluoride.

Claim 36

The process of claim 29 wherein said silicon oxide layer formed on said side walls of said mesa structures ranges in thickness from about 1000 to 1500 Å.

Claim 37

The process of claim 29 wherein said P-type dopant consists essentially of boron.