US4700214A
Expired / Lapsed
US
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Electrical circuitry
Assignee: Laserpath Corp
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Filing: 1987-05-20
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Granted: 1987-10-13
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Expires: 2007-05-20
Abstract
Abstract Electrical circuitry 32 is comprised of a plurality of layers 30, 100, each layer 30, 100 including one or more electrical pathways 36, 38, each layer 30, 100 also including insulation 34 for insulating at least part of one layer 30 from another layer 100. The pathways 36, 38 comprise repeating patterns 40, 42. Each pathway 36, 38 of each layer 30, 100 can communicate with the pathways 36, 38 of the next adjacent layers 30, 100. Some portions of the patterns 40, 42 which comprise the pathways 36, 38 of each layer 30, 100 can be at least partially aligned with some portion of the patterns 40, 42 of pathways 36, 38 of the other layers 30, 100. Other portions of the pathways 36, 38 of the layers 30, 100 remain unaligned. A pulse laser 134 can be used to sever unaligned portions of the pathways 36, 38 as appropriate to create the desired electrical circuitry 32. Components can be secured to the electrical circuitry as required. Further, such circuitry can be used in the construction of the final metallization layers of chips such as gate arrays.
Inventors
- 👤 Morgan Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:20
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H05K3/326; H05K1/00; H05K1/02; H05K1/0286; H05K1/0287; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/641; H05K1/11; H05K1/118; H05K2201/00; H05K2201/09; H05K2201/09009; H05K2201/091; H05K2201/10; H05K2201/10227; H05K2201/10295; H05K2201/10303; H05K2201/10431; H05K2201/1059; H05K2203/00; H05K2203/17; H05K2203/175; H05K3/0058; H05K3/306; H05K3/40; H05K3/4038; H05K3/4046; H05K3/46; H05K3/4611
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
323 words
An electrical circuit of an integrated circuit chip comprising: a first alyer having a plurality of first electrical pathways, each of said first electrical pathways having a plurality of first repeating patterns, each of said first repeating patterns including a plurality of mutually aligned first traces; wherein the first traces in one of said first electrical pathways are aligned with the first traces in another of said first electrical pathways such that all of said first traces are capable of being cut along a first cut path; said first layer further having a plurality of first electrical connecting pathways that interconnect said first repeating patterns of said first electrical pathways so as to form a first grid; a second layer located adjacent said first layer, said second layer having a plurality of second electrical pathways, each of said second electrical pathways having a plurality of second repeating patterns, each of said second repeating patterns including a plurality of mutually aligned second traces; wherein the second traces in one of said second electrical pathways are aligned with the second traces in another of said second electrical pathways such that all of said second traces are capable of being cut along a second cut path; said second layer further having a plurality of second electrical connecting pathways that interconnect said second repeating patterns of said second electrical pathways so as to form a second grid; said first cut path being aligned with said second cut path and said first traces being unaligned with said second traces such that any of said first traces and any of said second traces can be cut along said first and second cut paths without cutting any other of said first and second traces; communicating means for communicating between the first and second layers; and wherein said first traces (44, 46, and 66) are mutually substantially parallel and wherein said second traces (92, 94 and 96) are mutually substantially parallel.
Claim 2
Dependent Claim
323 words
An electrical circuit of an integrated circuit chip comprising: a first alyer having a plurality of first electrical pathways, each of said first electrical pathways having a plurality of first repeating patterns, each of said first repeating patterns including a plurality of mutually aligned first traces; wherein the first traces in one of said first electrical pathways are aligned with the first traces in another of said first electrical pathways such that all of said first traces are capable of being cut along a first cut path; said first layer further having a plurality of first electrical connecting pathways that interconnect said first repeating patterns of said first electrical pathways so as to form a first grid; a second layer located adjacent said first layer, said second layer having a plurality of second electrical pathways, each of said second electrical pathways having a plurality of second repeating patterns, each of said second repeating patterns including a plurality of mutually aligned second traces; wherein the second traces in one of said second electrical pathways are aligned with the second traces in another of said second electrical pathways such that all of said second traces are capable of being cut along a second cut path; said second layer further having a plurality of second electrical connecting pathways that interconnect said second repeating patterns of said second electrical pathways so as to form a second grid; said first cut path being aligned with said second cut path and said first traces being unaligned with said second traces such that any of said first traces and any of said second traces can be cut along said first and second cut paths without cutting any other of said first and second traces; communicating means for communicating between the first and second layers; and wherein said first traces (44, 46, and 66) are mutually substantially parallel and wherein said second traces (92, 94 and 96) are mutually substantially parallel.
Claim 3
Dependent Claim
15 words
The electrical circuit of claim 1 wherein said first and second electrical pathways are metalized.
Claim 4
Dependent Claim
40 words
The electrical circuit of claim 1 wherein said first and second cut paths are substantially straight lines (such as cut path (91) FIG. (1) and cut path (93) FIG. (2), which are superimposed as depicted at (113) in FIG. (5)).
Claim 5
Dependent Claim
33 words
The electrical circuit of claim 3 wherein said first cut path is substantially perpendicular to said first parallel traces; and wherein said second cut path is substantially perpendicular to said second parallel traces.
Claim 6
Dependent Claim
34 words
The electrical circuit of claim 1 wherein said first layer overlies said second layer and said first and second cut paths are aligned such that said first cut path overlies said second cut path.
Claim 7
Dependent Claim
18 words
The electrical circuit of claim 5 wherein none of said first traces overlie any of said second traces.
Claim 8
Dependent Claim
24 words
The electrical circuit of claim 1 and further including insulating means for insulating at least part of said first layer from said second layer.
Claim 9
Dependent Claim
23 words
The electrical circuit of claim 1 wherein the patterns on said first layer are substantially identical to the patterns on said second layer.
Claim 10
Dependent Claim
37 words
The electrical circuit of claim 1 wherein said first layer overlies said second layer, wherein none of said first traces overlie any of said second traces, and wherein said first cut path overlies said second cut path.
Claim 11
Dependent Claim
43 words
The electrical circuit of claim 1 wherein: the patterns on the first layer are substantially identical to the patterns on the second layer with the patterns on the second layer located at a position transitionally displaced from the patterns on the first layer.
Claim 12
Dependent Claim
43 words
The electrical circuit of claim 1 wherein: the patterns on the first layer are substantially identical to the patterns on the second layer with the patterns on the second layer located at a position rotationally displaced from the patterns on the first layer.
Claim 13
Dependent Claim
372 words
An electrical circuit of an integrated circuit chip comprising: a first layer having a plurality of first electrical pathways, each of said first electrical pathways having a plurality of first repeating patterns, each of said first repeating patterns including a plurality of mutually aligned first traces; wherein the first traces in one of said first electrical pathways are aligned with the first traces in another of said first electrical pathways such that all of said first traces are capable of being cut along a first cut path; said first layer further having a plurality of first electrical connecting pathways that interconnect said first repeating patterns of said first electrical pathways so as to form a first grid; a second layer located adjacent said first layer, said second layer having a plurality of second electrical pathways, each of said second electrical pathways having a plurality of second repeating patterns, each of said second repeating patterns including a plurality of mutually aligned second traces; wherein the second traces in one of said second electrical pathways are aligned with the second traces in another of said second electrical pathways such that all of said second traces are capable of being cut along a second cut path; said second layer further having a plurality of second electrical connecting pathways that interconnect said second repeating patterns of said second electrical pathways so as to form a second grid; said first cut path being aligned with said second cut path and said first traces being unaligned with said second traces such that any of said first traces and any of said second traces can be cut along said first and second cut paths without cutting any other of said first and second traces; communicating means for communicating between the first and second layers; wherein said first layer overlies said second layer, wherein none of said first traces overlie any of said second traces, and wherein said first cut path overlies said second cut path; and further including window means provided in one of said first and second layers for allowing access to said traces of said other of said first and second layers along said first and second cut paths to facilitate a selectable severing of the trace.
Claim 14
Dependent Claim
372 words
An electrical circuit of an integrated circuit chip comprising: a first layer having a plurality of first electrical pathways, each of said first electrical pathways having a plurality of first repeating patterns, each of said first repeating patterns including a plurality of mutually aligned first traces; wherein the first traces in one of said first electrical pathways are aligned with the first traces in another of said first electrical pathways such that all of said first traces are capable of being cut along a first cut path; said first layer further having a plurality of first electrical connecting pathways that interconnect said first repeating patterns of said first electrical pathways so as to form a first grid; a second layer located adjacent said first layer, said second layer having a plurality of second electrical pathways, each of said second electrical pathways having a plurality of second repeating patterns, each of said second repeating patterns including a plurality of mutually aligned second traces; wherein the second traces in one of said second electrical pathways are aligned with the second traces in another of said second electrical pathways such that all of said second traces are capable of being cut along a second cut path; said second layer further having a plurality of second electrical connecting pathways that interconnect said second repeating patterns of said second electrical pathways so as to form a second grid; said first cut path being aligned with said second cut path and said first traces being unaligned with said second traces such that any of said first traces and any of said second traces can be cut along said first and second cut paths without cutting any other of said first and second traces; communicating means for communicating between the first and second layers; wherein said first layer overlies said second layer, wherein none of said first traces overlie any of said second traces, and wherein said first cut path overlies said second cut path; and further including window means provided in one of said first and second layers for allowing access to said traces of said other of said first and second layers along said first and second cut paths to facilitate a selectable severing of the trace.
Claim 15
Dependent Claim
16 words
The electrical circuit of claim 12 wherein said window means is transparent to an energy beam.
Claim 16
Dependent Claim
14 words
The electrical circuit of claim 12 wherein said window means includes cut out portions.
References Cited (Backward Citations)
US3500346A
Cited
GB1157432A
Cited
US3398326A
Cited
US3564115A
Cited
US3646670A
Cited
US3605063A
Cited
US3660726A
Cited
US3876822A
Cited
US3859711A
Cited
US3953924A
Cited
US4197555A
Cited
US4298770A
Cited
US4432037A
Cited
US4524239A
Cited
US4438660A
Cited
US4506442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-12 | 1991-04-13 | 1991-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-12 | 1995-04-13 | 1995-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-12 | 1999-04-13 | 1999-10-13 | $7700.00 | Window Closed / Lapsed |