Non-volatile random access memory cell

Claim 2

A non-volatile random access memory cell comprising: a volatile memory cell for storing a datum comprising flip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, and a first capacitor connected to said first node; and a non-volatile memory cell comprising a second capacitor, operatively connected to said second node, having a capacitance larger than that of said first capacitor, a memory transistor having a floating gate, connected between said second node and said second capacitor, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate, a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate, means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor, a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, and a second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum, said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively.

Claim 3

A non-volatile random access memory cell comprising: a volatile memory cell for storing a datum comprising flip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, and a first capacitor connected to said first node; and a non-volatile memory cell comprising a memory transistor having a floating gate, connected to said second node, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate, a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate, means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor, a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, a second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum, and a third transistor, connected between said second node and said memory transistor, for switching the connection between said second node and said memory transistor, said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively.

Claim 4

A non-volatile random access memory cell comprising: a volatile memory cell for storing a datum comprising flip-flop circuit having a first and second nodes on which complementary signals corresponding to the stored datum are output, and a first capacitor connected to said first node; and a non-volatile memory cell comprising a memory transistor having a floating gate, connected to said second node, said memory transistor acting as a switch in accordance with the polarity of the charge stored at said floating gate, a capacitor circuit comprising a tunnel capacitor operatively connected to said floating gate, means, operatively connected to said capacitor circuit, for applying a writing voltage having an amplitude large enough to cause a tunnel current to flow through said tunnel capacitor, a first transistor, operatively connected to said second node and to said capacitor circuit, for controlling the polarity of said tunnel current in accordance with said stored datum, said first transistor generating an output in response to one of said complementary signals at said second node, a second transistor, operatively connected to said capacitor circuit receiving the output of said first transistor, for controlling the polarity of said tunnel current in accordance with said stored datum, and a third transistor, connected between said second node and said memory transistor, for switching the connection between said second node and said memory transistor, said first and second transistors cooperatively controlling the polarity of the tunnel current to flow through said tunnel capacitor when said writing voltage is applied to said capacitor circuit, one of said first and second transistors being ON and the other being OFF when said tunnel current is to be flown, said polarity of the tunnel current being controlled to be in one of two directions opposite to each other depending on which one of said first and second transistors is ON, said two directions being such that said floating gate is provided with one of negative and positive charges by said tunnel current in one of said two directions, respectively.

Claim 5

A non-volatile random access memory cell according to claim 1 or 2, wherein said capacitor circuit of said non-volatile memory cell further comprising a third capacitor, one side electrode thereof being connected to said writing voltage and the other side electrode thereof being connected to one side electrode of said tunnel capacitor, the source of said first transistor, and the gate of said second transistor, and a capacitor module having a common electrode, a first electrode forming a fourth capacitor with said common electrode, and a second electrode forming a fifth capacitor with said common electrode, said first electrode being connected to said writing voltage, said common electrode being connected to the source of said second transistor, and said second electrode being connected to said floating gate and the other side electrode of said tunnel capacitor.

Claim 6

A non-volatile random access memory cell according to claim 1 or 2, wherein said first transistor operates under a power supply voltage applied to said non-volatile random access memory cell against earth potential and said fist transistor has the gate connected to said second node and the drain connected to said earth potential.

Claim 7

A non-volatile random access memory cell according to claim 1 or 2, wherein said second transistor operates under a power supply voltage applied to said non-volatile random access memory cell against earth potential and said second transistor has the drain connected to said earth potential.

Claim 8

A non-volatile random access memory cell according to claim 1 or 2, wherein said volatile memory cell is a volatile static type random access memory cell and said non-volatile memory cell is a non-volatile electrically erasable programmable read-only memory cell.