MOS read-only memory systems

Claim 2

An MOS read-only-memory system comprising: (a) a memory matrix having a plurality of memory cells, a plurality of data lines and a plurality of word lines; said data lines and said word lines being arranged in a matrix form, each of said memory cells comprising a MOS FET which has a gate electrode connected to each of said word lines, a source electrode connected to each of said data lines and a drain electrode connected to a common line; said common line being connected to a high potential of a power supply; (b) a word line decoder for selecting one of said word lines in response to a row address signal; (c) a multiplexer connected to said data lines of said memory matrix and including a plurality of MOS FETs; (d) a data line decoder for activating one of said plurality of MOS FETs in response to a column address signal to select one of said data lines; and (e) a read and sense circuit having a current input terminal connected to said multiplexer and an output terminal for detecting and amplifying a current from said multiplexer through a specific memory cell in said memory matrix selected by said row address signal and said column address signal to deliver a data signal to said output terminal.

Claim 3

An MOS ROM system comprising: (a) a memory matrix having a plurality of memory cells, a plurality of data lines and a plurality of word lines, said data lines and said word lines being arranged in a matrix form, each of said memory cells comprising a MOS FET which has a gate electrode connected to each of said word lines, a source electrode connected to each of said data lines and a drain electrode connected to a first common line; said common line being connected to a high potential of a first supply; (b) a word line decoder for selecting one of said word lines in response to a row address signal; (c) a multiplexer connected to said data lines of said memory matrix and including a plurality of MOS FETs; (d) a data line decoder for activating one of said plurality of MOS FETs in response to a column address signal to select one of said data lines; (e) a plurality of load means each connected between each of said data lines and a second common line for suppressing a voltage drop on unselected data lines during a read operation; and (f) a read and sense circuit having a current input terminal connected to said multiplexer and an output terminal for detecting and amplifying a current from said multiplexer through a specific memory cell in said memory matrix selected by said row address signal and said column address signal to deliver a data signal to said output terminal.

Claim 4

An MOS ROM system comprising: (a) a memory matrix having a plurality of memory cells, a plurality of data lines and a plurality of word lines, said data lines and said word lines being arranged in a matrix form, each of said memory cells comprising a MOS FET which has a gate electrode connected to each of said word lines, a source electrode connected to each of said data lines and a drain electrode connected to a first common line; said common line being connected to a high potential of a first supply; (b) a word line decoder for selecting one of said word lines in response to a row address signal; (c) a multiplexer connected to said data lines of said memory matrix and including a plurality of MOS FETs; (d) a data line decoder for activating one of said plurality of MOS FETs in response to a column address signal to select one of said data lines; (e) a plurality of load means each connected between each of said data lines and a second common line for suppressing a voltage drop on unselected data lines during a read operation; and (f) a read and sense circuit having a current input terminal connected to said multiplexer and an output terminal for detecting and amplifying a current from said multiplexer through a specific memory cell in said memory matrix selected by said row address signal and said column address signal to deliver a data signal to said output terminal.

Claim 5

An MOS ROM system according to claim 2, wherein said first and second common lines are supplied with a high potential of a power supply.

Claim 6

An MOS ROM system according to claim 2, further including voltage reducing means connected between a power supply and both said first and second common lines for providing a reduced high potential such that there is an absence of an inversion layer under a gate insulating layer of each of unselected memory cells associated with a selected word line during a read operation.

Claim 7

An MOS ROM system according to claim 4, wherein said voltage reducing means comprises a plurality of MOS FETs which are serially connected with each other, each of said plurality of MOS FETs having its source electrode and its drain electrode connected to its gate electrode.

Claim 8

An MOS ROM system according to claim 4, wherein said voltage reducing means comprises a depletion MOS FET having a drain electrode connected to said power supply, a gate electrode and a source electrode connected to said gate electrode, a first enhancement MOS FET having a gate electrode, a drain electrode connected to said source electrode of said depletion MOS FET and a source electrode connected to a low fixed potential of said power supply, and a second enhancement MOS FET having a drain electrode connected to a high fixed potential of said power supply, a gate electrode connected to said source electrode of said depletion MOS FET, and a source electrode connected to said current input terminal and to said gate electrode of said first enhancement MOS FET.

Claim 9

An MOS ROM system according to claim 2, wherein said read and sense circuit comprises: (a) a current sensing means connected to said current input terminal for providing a reference voltage and a voltage obtained by converting a current from said multiplexer, said current sensing means comprising a current to voltage converter connected to said current input terminal for converting said current from said multiplexer into a voltage, and a reference voltage generating circuit connected to said current to voltage converter; (b) a differential amplifier connected to said current sensing means for amplifying a voltage difference between said reference voltage and said converted voltage from said current to voltage converter; and (c) an output circuit connected to said differential amplifier for providing said data signal to said output terminal.

Claim 10

An MOS ROM system according to claim 7, wherein said current to voltage converter in said current sensing means comprises a first enhancement MOS FET having a gate electrode, a drain electrode connected to said current input terminal and a source electrode connected to a low fixed potential of a power supply, a second enhancement MOS FET having a source electrode connected to said current input terminal, a drain electrode connected to said gate electrode of said first MOS FET and a gate electrode connected to said reference voltage generating circuit, and a depletion MOS FET having a drain electrode connected to a high fixed potential of said power supply, a source electrode connected to said drain electrode of said second MOS FET and a gate electrode connected to said drain electrode of said second MOS FET and to said gate electrode of said third MOS FET in said differential amplifier.

Claim 11

An MOS ROM system according to claim 8, wherein said reference voltage generating circuit comprises a first enhancement MOS FET having a source electrode connected to said low fixed potential, a drain electrode and a gate electrode connected to said gate electrode of said second MOS FET in said current to voltage converter, a second enhancement MOS FET having a source electrode connected to said drain electrode of said first MOS FET, a drain electrode and a gate electrode connected to said gate electrode of said first MOS FET and to said drain electrode, and a depletion MOS FET having a drain electrode connected to said high fixed potential, a source electrode connected to said drain electrode of said second MOS FET and a gate electrode connected to said gate electrode of said second MOS FET.

Claim 12

An MOS ROM system according to claim 8, wherein said reference voltage generating circuit comprises a first enhancement MOS FET having a source electrode connected to said low fixed potential, a gate electrode connected to the gate electrode of said second MOS FET in said current to voltage converter and a drain electrode connected to a data line associated with dummy memory cells, a second enhancement MOS FET having a source electrode connected to said drain electrode of said first MOS FET, a drain electrode and a gate electrode of said first MOS FET, and a depletion MOS FET having a drain electrode connected to said high fixed potential, a source electrode connected to said drain electrode of said second MOS FET and a gate electrode connected to said gate electrode of said second MOS FET.

Claim 13

An MOS ROM system according to claim 7, wherein said current to voltage converter in said current sensing means comprises a first N type enhancement MOS FET having a gate electrode connected to said differential amplifier, a drain electrode connected to said current input terminal and a source electrode connected to a low fixed potential of a power supply, a second N type enhancement MOS FET having a source electrode connected to said current input terminal, a drain electrode connected to said gate electrode of said first N type MOS FET and a gate electrode, and a P type enhancement MOS FET having a source electrode connected to a high fixed potential, a drain electrode connected to said drain electrode of said second N type MOS FET, and a gate electrode connected to said gate electrode of said second N type MOS FET; and wherein said reference voltage generating circuit comprises a first N type enhancement MOS FET having a source electrode connected to said low fixed potential, a drain electrode connected to a data line associated with memory dummy cells, and a gate electrode connected to said gate electrode of said second N type MOS FET in said current to voltage converter, a second N type MOS FET having a drain electrode, a source electrode connected to said drain electrode of said first N type MOS FET, and a gate electrode connected to said gate electrode of said first N type MOS FET, a P type enhancement MOS FET having a source electrode connected to said high fixed potential, a gate electrode connected to said gate electrode of said second N type MOS FET, and a source electrode connected to said gate electrode and to said drain electrode of said second N type MOS FET and to said differential amplifier.

Claim 14

An MOS ROM system according to claim 7, wherein said differential amplifier comprises a first enhancement MOS FET having a drain electrode, a source electrode connected to a low fixed potential of a power supply, and a gate electrode to a high potential of said power supply, a second enhancement MOS FET having a gate electrode connected to said reference voltage generating circuit, a drain electrode, and a source electrode connected to said drain electrode of said first MOS FET, a third enhancement MOS FET having a drain electrode, a gate electrode connected to said converter, and a source electrode connected to said drain electrode of said MOS FET, a first depletion MOS FET having a drain electrode connected to said high fixed potential, a gate electrode and a source electrode connected to said gate electrode and to said drain electrode of said second MOS FET, and a second depletion MOS FET having a drain electrode connected to said drain electrode of said third MOS FET and a gate electrode connected to said source electrode.