Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: at least two NPN transistors whose bases and emitters are connected to the ground and whose collectors are connected to an input terminal; one of said NPN transistors having a lower breakdown starting voltage and a higher breakdown maintaining voltage than those of the other of said NPN transistors; and an input portion which has a breakdown maintaining voltage at a high surge voltage breakdown which occurs due to an application of a high surge voltage input to said input terminal which is lower than that at a low input voltage breakdown which occurs due to an application of a low surge voltage or an input voltage which rises up gradually.

Claim 3

A semiconductor integrated circuit device as defined in claim 1, wherein a resistance component serially connected to said NPN transistor having a higher breakdown maintaining voltage is larger than the resistance of said NPN transistor having a lower breakdown maintaining voltage.

Claim 4

A semiconductor integrated circuit device as defined in claim 1, wherein said input portion has a P type semiconductor substrate, a plurality of N type embedded layers produced on said substrate apart from each other, an N type epitaxial layer produced on said N type embedded layers, an oxide film produced on said semiconductor substrate to separate said epitaxial layers from each other, P layers produced on said semiconductor substrate directly below said oxide film to have a higher impurity density than that of said semiconductor substrate, P layers produced in said epitaxial layers, and N layers produced in said P layers, and said N type epitaxial layers are used as the collector of said lower breakdown maintaining voltage NPN transistor at the input portion, said P layer in said epitaxial layer and said N layer in said P layer are used as the base and the emitter thereof, respectively, said P layers produced in said semiconductor substrate direct below said oxide film is used as the base of said higher breakdown maintaining voltage NPN transistor, and said N type embedded layers at the both sides of said P layer is used as the emitter and the collector thereof, respectively.