Automatic synchronous/asynchronous modem

Claim 2

A circuit for interposition between a communication line and a processor, said communication line having data transmission thereon, said circuit comprising means for monitoring each new data transmission on said communication line for a preset interval at the start of said new data transmission, means operable under control of said monitoring means for detecting whether a particular new data transmission is in synchronous format or in asynchronous format, and means for providing a first signal when a new one of said data transmissions is detected as being synchronous and for providing a different signal when said new data transmission is detected as being asynchronous.

Claim 3

The invention set forth in claim 1 wherein said monitoring means includes means beginning with any data bit for breaking said monitored transmission into data bytes having n data bits each, means for comparing successive ones of said data bytes during said preset interval, means for counting successive ones of said data bytes which have all like data bits in the same relative positions within successive ones of said compared data bytes, and means for providing said first signal when said counting means reaches a preset number within said preset interval.

Claim 4

The invention set forth in claim 2 further comprising means for resetting said counting means upon detecting data bytes having certain preestablished ones of said data bit combinations.

Claim 5

The invention set forth in claim 3 wherein n equals eight.

Claim 6

The invention set forth in claim 1 wherein said transmission includes an initialization portion followed by an active data transmission portion, and wherein said preset interval occurs within the first 5 seconds of said transmission portion.

Claim 7

The invention set forth in claim 1 wherein said circuit further includes means for processing either said synchronous or said asynchronous data transmission, and means responsive to said signals for enabling said processing means.

Claim 8

The invention set forth in claim 1 further comprising means for providing said signals to said processor.

Claim 9

A signal processing device for use between data transmitting and data receiving devices, said signal processing device operable for controlling data transmissions between said data devices in either of two transmission modes, said modes characterized by data patterns within said transmission unique to said transmission mode, said signal processing device comprising means for establishing a preset interval, means for establishing a series of data bytes each said byte having n data bits, means for examining any said established bytes, means for comparing successive ones of said examined data bytes to determine if a certain preset number m of said compared data bytes are the same, and means for providing a first signal indicative of one of said transmission modes to a receiving data transmission device upon a determination that said preset number m of consecutive data bytes is the same within said preset interval.

Claim 10

A signal processing device for use between data transmitting and data receiving devices, said signal processing device operable for controlling data transmissions between said data devices in either of two transmission modes, said modes characterized by data patterns within said transmission unique to said transmission mode, said signal processing device comprising means for establishing a preset interval, means for establishing a series of data bytes each said byte having n data bits, means for examining any said established bytes, means for comparing successive ones of said examined data bytes to determine if a certain preset number m of said compared data bytes are the same, and means for providing a first signal indicative of one of said transmission modes to a receiving data transmission device upon a determination that said preset number m of consecutive data bytes is the same within said preset interval.

Claim 11

The invention set forth in claim 8 wherein said number of data bits within each said data byte is 8 and wherein said establishing means begins with any said data bit in said transmission.

Claim 12

The invention set forth in claim 9 wherein said preset interval is 5 seconds at the beginning of each new transmission between data transmitting and receiving devices.

Claim 13

The invention set forth in claim 9 further comprising means for inhibiting the enabling of said providing means upon the detection of certain preestablished data bit combinations within said compared data byte.

Claim 14

The invention set forth in claim 8 wherein said device includes means for uniquely configuring said device to control data transmission in only one of said two modes, and means controlled by said first signal providing means for controlling said configuring means.