US4717940A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS controlled gate turn-off thyristor
Assignee: Toshiba Corp
•
Filing: 1987-02-13
•
Granted: 1988-01-05
•
Expires: 2007-02-13
Abstract
Abstract An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.
Inventors
- 👤 Takashi Shinohe
- 👤 Katsuhiko Takigami
- 👤 Hiromichi Ohashi
- 👤 Akio Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:10
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/148; H10D18/00; H10D18/60; H10D18/65; H10D18/655; H10D62/17; H10D62/192; H10D62/206
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
167 words
An MIS controlled gate turn-off thyristor comprising: a first emitter layer of a first conductivity type; a first base layer of a second conductivity type forming a pn junction relative to the first emitter layer; a second base layer of the first conductivity type forming a pn junction relative to the first base layer; a low impurity concentration layer formed on the second base layer; a second emitter layer of the second conductivity type formed such that it extends, through the low impurity concentration layer, into the second base layer; first and second ohmic electrodes in contact with the first and second emitter layers, respectively; and an MIS transistor formed in the surface portion of the low impurity concentration layer and having source and drain regions, one of which is connected to the second ohmic electrode and the other of which is connected through a low resistance layer to the second base layer to allow the second base layer to be short-circuited to the second emitter layer.
Claim 2
Dependent Claim
167 words
An MIS controlled gate turn-off thyristor comprising: a first emitter layer of a first conductivity type; a first base layer of a second conductivity type forming a pn junction relative to the first emitter layer; a second base layer of the first conductivity type forming a pn junction relative to the first base layer; a low impurity concentration layer formed on the second base layer; a second emitter layer of the second conductivity type formed such that it extends, through the low impurity concentration layer, into the second base layer; first and second ohmic electrodes in contact with the first and second emitter layers, respectively; and an MIS transistor formed in the surface portion of the low impurity concentration layer and having source and drain regions, one of which is connected to the second ohmic electrode and the other of which is connected through a low resistance layer to the second base layer to allow the second base layer to be short-circuited to the second emitter layer.
Claim 3
Dependent Claim
50 words
The MIS controlled gate turn-off thyristor according to claim 1, in which a high impurity concentration layer of the second conductivity type continuous with said second emitter is formed at an interface between said second base layer under an area of said MIS transistor and said low impurity concentration layer.
Claim 4
Dependent Claim
52 words
The MIS controlled gate turn-off thyristor according to claim 1, in which a high impurity concentration layer of the second conductivity type continuous with said second emitter layer is formed locally at an interface of said second base layer under an area of said MIS transistor and said low impurity concentration layer.
Claim 5
Dependent Claim
60 words
The MIS controlled gate turn-off thyristor according to claim 1, in which a high impurity concentration layer of the second conductivity type is formed over a whole interface between said second base layer and said low impurity concentration layer such that it is continuous with said second emitter layer and has a plurality of windows at said low resistance layer.
Claim 6
Dependent Claim
52 words
The MIS controlled gate turn-off thyristor according to claim 1, in which a high impurity concentration layer of the second conductivity type is formed at an interface between said second base layer and said low impurity concentration layer such that it is continuous and has a pattern of a plurality of stripes.
Claim 7
Dependent Claim
49 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low impurity concentration layer is of the first conductivity type and said MIS transistor is of a second channel conductivity type where the surface portion of said low impurity concentration layer acts as a channel region.
Claim 8
Dependent Claim
94 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low impurity concentration layer is comprised of a first low impurity concentration layer of the first conductivity type formed on a whole surface of said second base layer and a second low impurity concentration layer of the second conductivity type selectively formed in the surface portion of said first low impurity concentration layer, and said MIS transistor is of a first channel conductivity type in which the surface portion of said second low impurity concentration layer acts as a channel region.
Claim 9
Dependent Claim
50 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low impurity concentration layer is of the second conductivity type and said MIS transistor is of the first channel conductivity type in which a surface portion of said low impurity concentration layer acts as a channel region.
Claim 10
Dependent Claim
94 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low impurity concentration layer is comprised of a first low impurity concentration layer of the second conductivity type formed on a whole surface of said second base layer and a second low impurity concentration layer of the first conductivity type selectively formed in the surface portion of said first low impurity concentration layer and said MIS transistor is of the second channel conductivity type in which the surface portion of said second low impurity concentration layer acts as a channel region.
Claim 11
Dependent Claim
28 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low resistance layer is a high impurity concentration semiconductor layer of the first conductivity type.
Claim 12
Dependent Claim
43 words
The MIS controlled gate turn-off thyristor according to claim 1, in which said low resistance layer is formed of an on-gate electrode in ohmic contact with said low resistance layer and with one of said source and drain regions of said MIS transistor.
References Cited (Backward Citations)
US4062032A
Cited
US4224634A
Cited
JPS5366384A
Cited
US4177478A
Cited
JPS54120588A
Cited
US4291325A
Cited
EP0028797A2
Cited
JPS5680165A
Cited
JPS5778172A
Cited
US4574296A
Cited
JPS5947469A
Cited
JPS609668A
Cited
DE3447220A1
Cited
US4587713A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |