Semiconductor memory device adapted to carry out operation test

Claim 2

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; column gates connected to said columns of bit lines; row and column decoders, operatively connected to said cell matrix, for receiving and decoding the selection signals and for performing a selection of all of one of said rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals for said semiconductor memory device; and line selection checking means, operatively connected to said cell matrix and said column gates, for forming logic gate circuit means including a plurality of transistors, the gates of said transistors being respectively connected to one of said rows of word lines and columns of bit lines through said column gates, and including one of a voltage and current detection portion operatively connected to one of said plurality of pads for detecting one of an output voltage and current of said line selection checking means.

Claim 3

A device according to claim 1, wherein said line selection checking means is a line selection checking circuit for checking the selection of all of one of said rows of word lines and columns of bit lines.

Claim 4

A device according to claim 2, wherein said line selection checking means comprises: a first series sequence of transistors, operatively connected to said rows of word lines, for receiving gate signals from all of said word lines; a second series of transistors, operatively connected to said columns of bit lines, for receiving gate signals from all of said bit lines, said first and second series sequences of transistors connected in parallel; and a switching transistor operatively connected to said first and second series sequences of transistors.

Claim 5

A device according to claim 3, further comprising: a bus line operatively connected to an electrode of said switching transistor; and an output buffer circuit connected between said bus line and one of said plurality of output pads.

Claim 6

A device according to claim 3, further comprising: a high voltage detection circuit operatively connected to one of said plurality of pads; and an inverter operatively connected between said high voltage detection circuit and a gate of said switching transistor.

Claim 7

A device according to claim 1, wherein said line selection checking means includes a plurality of line selection checking circuits, each of said line selection checking circuits checking the selection of a group of one of said rows of word lines and columns of bit lines.

Claim 8

A device according to claim 6, wherein each of said plurality of line selection checking circuits comprises: a first series sequence of transistors, operatively connected to said rows of word lines, for receiving gate signals from a group of said word lines; a second series sequence of transistors, operatively connected to said columns of bit lines, for receiving gate signals from a group of said bit lines, said first and second series sequences of transistors connected in parallel; and a switching transistor operatively connected to said first and second series sequences of transistors.

Claim 9

A device according to claim 7, further comprising: an output buffer operatively connected to one of said plurality of pads; a bus line operatively connected between said output buffer and an electrode of said switching transistor.

Claim 10

A device according to claim 7, further comprising: a high voltage detection circuit operatively connected to one of said plurality of pads; and an inverter operatively connected between said high voltage detection circuit and a gate of said switching transistor.

Claim 11

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; transfer gates operatively connected to said columns of bit lines; a sense amplifier operatively connected to said transfer gates; row and column decoders, operatively connected to said rows of word lines and columns of bit lines, for receiving and decoding the selection signals and for carrying out a selection of all of one of said rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals to said semiconductor memory device, a number of said pads being connected to said sense amplifier; and line selection checking means, operatively connected to said cell matrix, for forming logic gate circuit means including a plurality of transistors having gates respectively, operatively connected to one of said rows of word lines and columns of bit lines, said line selection checking means including one of a voltage and current detection portion for detecting an output voltage of said line selection checking circuit.

Claim 12

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; transfer gates operatively connected to said columns of bit lines; a sense amplifier operatively connected to said transfer gates; row and column decoders, operatively connected to said rows of word lines and columns of bit lines, for receiving and decoding the selection signals and for carrying out a selection of all of one of said rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals to said semiconductor memory device, a number of said pads being connected to said sense amplifier; and line selection checking means, operatively connected to said cell matrix, for forming logic gate circuit means including a plurality of transistors having gates respectively, operatively connected to one of said rows of word lines and columns of bit lines, said line selection checking means including one of a voltage and current detection portion for detecting an output voltage of said line selection checking circuit.

Claim 13

A device according to claim 10, wherein said line selection checking means includes an output node, said device further comprising a switching transistor operatively connected between said output node of said line selection checking means and said sense amplifier.

Claim 14

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; column gates connected to said columns of bit lines; row and column decoders, operatively connected to said cell matrix, for receiving and decoding the selection signals and for performing a selection of a group of one of said word rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals for said semiconductor memory device; and line selection checking means, operatively connected to said cell matrix and said column gates, for forming logic gate circuit means including a plurality of transistors having gates connected to one of said group of said rows of word lines and columns of bit lines selected by said row and column decoders, and including one of a voltage and current detection portion operatively connected to one of said plurality of pads for detecting one of an output voltage and current of said line selection checking means.

Claim 15

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; column gates connected to said columns of bit lines; row and column decoders, operatively connected to said cell matrix, for receiving and decoding the selection signals and for performing a selection of a group of one of said word rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals for said semiconductor memory device; and line selection checking means, operatively connected to said cell matrix and said column gates, for forming logic gate circuit means including a plurality of transistors having gates connected to one of said group of said rows of word lines and columns of bit lines selected by said row and column decoders, and including one of a voltage and current detection portion operatively connected to one of said plurality of pads for detecting one of an output voltage and current of said line selection checking means.

Claim 16

A device according to claim 12, wherein said line selection checking means is a line selection checking circuit for checking the selection of said group of said rows of word lines and columns of bit lines.

Claim 17

A device according to claim 13, wherein said line selection checking means comprises: a first series sequence of transistors, operatively connected to said rows of word lines, for receiving gate signals from all of said word lines; a second series sequence of transistors, operatively connected to said columns of bit lines, for receiving gate signal from all of said bit lines, said first and second series sequences of transistors connected in parallel; and a switching transistor operatively connected to said first and second series sequences of transistors.

Claim 18

A device according to claim 14, further comprising: a bus line operatively connected to an electrode of said switching transistor; and an output buffer circuit connected between said bus line and one of said plurality of output pads.

Claim 19

A device according to claim 14, further comprising: a high voltage detection circuit operatively connected to one of said plurality of pads; and an inverter operatively connected between said high voltage detection circuit and a gate of said switching transistor.

Claim 20

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; transfer gates operatively connected to said columns of bit lines; a sense amplifier operatively connected to said transfer gate; row and column decoders, operatively connected to said rows of word lines and columns of bit lines, for receiving and decoding the selection signals and for carrying out a selection of a group of one of said rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals to said semiconductor memory device, a number of said pads being connected to said sense amplifier; and line selection checking means, operatively connected to said cell matrix, for forming a logic gate circuit means including a plurality of transistors having gates respectively, operatively connected to one of said rows of word lines and columns of bit lines selected by said row and column decoders, and said line selection checking means including one of a voltage and current detection portion for detecting an output voltage of said line selection checking circuit.

Claim 21

A semiconductor memory device, operatively connected to receive selection signals, for performing a test operation for testing said semiconductor memory device, comprising: a cell matrix having a memory cell array including: rows of word lines; and columns of bit lines intersecting said rows of word lines; transfer gates operatively connected to said columns of bit lines; a sense amplifier operatively connected to said transfer gate; row and column decoders, operatively connected to said rows of word lines and columns of bit lines, for receiving and decoding the selection signals and for carrying out a selection of a group of one of said rows of word lines and columns of bit lines; a plurality of pads, operatively connected to said row and column decoders, for providing one of input and output terminals to said semiconductor memory device, a number of said pads being connected to said sense amplifier; and line selection checking means, operatively connected to said cell matrix, for forming a logic gate circuit means including a plurality of transistors having gates respectively, operatively connected to one of said rows of word lines and columns of bit lines selected by said row and column decoders, and said line selection checking means including one of a voltage and current detection portion for detecting an output voltage of said line selection checking circuit.

Claim 22

A device according to claim 17, wherein said line selection checking means includes an output node, said device further comprising a switching transistor operatively connected between said output node and said sense amplifier.