Priority resolution in bus orientated computer systems

Claim 1

A digital computer system for resolving priority between a plurality N of subsystems which require access to a shared resource, the priority being determined by an n-bit priority code, where n>1, ascribed to each subsystem, and where the n bits of each priority code each possess a different significance, the system comprising: an open-collector bus having n lines, each said line adapted to have assume a state representing a logic value, each one of said n lines corresponding to each of said n bits of the priority code; a plurality N of logic circuits, one of which being connected to each of the N subsystems and each of which having n stages, each said stage corresponding to a bit of a priority code and connected to a line of the open collector bus corresponding to a same bit of the priority code, the stages being connected in series with one another in a descending order of significance; and means for applying each bit of the priority code of each subsystem to a corresponding stage of an associated logic circuit of said subsystem, bits of the priority code addressing said logic circuit such that a most significant bit of the priority code is addressable to a first stage of the logic circuit and a least significant bit of the priority code is addressable to a nth stage; wherein a first stage of each said subsystem comprises means for applying said most significant bit to a corresponding line of the open collector bus, means for comparing a value of said most significant bit with a logic value of said corresponding line and means for selectively inhibiting/enabling, according to a pre-determined criterion, the next stage of the logic circuit, to apply a next most significant bit to a corresponding line of the open-collector bus; and wherein each stage subsequent to said first stage of each said subsystem comprises means for comparing, when enabled by said inhibiting/enabling means of a previous stage, logic values of a corresponding priority code bit and a corresponding line of the open-collector bus and means for inhibiting/enabling a next stage of the logic circuit, enable/inhibit instructions thereby rippling through each logic circuit to said nth stage, after which only one circuit is enabled, and the subsystem connected to said logic circuit gaining access to the shared resource.