US4722075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Equalized biased array for PROMS and EPROMS
Assignee: Texas Instruments Inc
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Filing: 1985-10-15
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Granted: 1988-01-26
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Expires: 2005-10-15
Abstract
Abstract An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V T above V BIAS . Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V T about V BIAS . The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
Inventors
- 👤 Jeffrey K. Kaszubinski
- 👤 David D. Wilmoth
- 👤 Timmie M. Coffman
- 👤 John F. Schreck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:00
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C16/00; G11C16/02; G11C16/06; G11C16/24
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
100 words
A biasing network for an array of semiconductor memory transistors coupled between associated bit and secure lines, comprising: a bias line; biasing means coupled to said bias line for biasing the latter to a preselected voltage V bias lower than a supply voltage V cc ; bit means coupled between said bias line and said bit lines for transmitting the voltage V bias during a read cycle to said bit lines; source means coupled between said bias line and said source lines for transmitting the voltage V bias to each source line when its corresponding memory transistor is not selected.
Claim 2
Dependent Claim
100 words
A biasing network for an array of semiconductor memory transistors coupled between associated bit and secure lines, comprising: a bias line; biasing means coupled to said bias line for biasing the latter to a preselected voltage V bias lower than a supply voltage V cc ; bit means coupled between said bias line and said bit lines for transmitting the voltage V bias during a read cycle to said bit lines; source means coupled between said bias line and said source lines for transmitting the voltage V bias to each source line when its corresponding memory transistor is not selected.
Claim 3
Dependent Claim
43 words
A biasing network according to claim 1, wherein said bit means is a plurality of bit transistors whose source-to-drain paths are coupled between said bias line and corresponding respective bit lines and whose gates are coupled to the supply voltage V cc .
Claim 4
Dependent Claim
63 words
A biasing network according to claim 2, wherein said source means is a plurality of source transistors whose source-to-drain paths are coupled between said bias line and corresponding respective source lines and whose gates are coupled to the complement of a ground select control signal operative to make said source transistors conductive when said source lines have a high impedance path to ground.
Claim 5
Dependent Claim
47 words
A biasing network according to claim 3, wherein said biasing means is a supply transistor whose source-to-drain path is coupled between the supply voltage V cc and said bias line and whose gate is coupled to a reference voltage REF lower in magnitude than V cc .
Claim 6
Dependent Claim
68 words
A biasing network according to claim 4, wherein said bias line is coupled to ground through a bleed transistor whose channel impedance when conductive is sufficiently greater than that of said supply transistor when conductive so that the voltage V bias is approximately equal to reference voltage REF less the threshold voltage of said supply transistor and whose gate is connected to the supply voltage V cc .
Claim 7
Dependent Claim
70 words
A biasing network according to claim 5, including a sense amplifier having one input coupled to said bit lines through a select transistor and another input coupled to a voltage reference source of a value midway between the voltage on said one input when a selected memory transistor is in a programmed state and the voltage on said one input when the selected memory transistor is in a non-programmed state.
Claim 8
Independent Claim
49 words
A method of biasing an array of semiconductor memory transistors of a type having respective bit and source lines, comprising: establishing a predetermined bias voltage; and transmitting said bias voltage onto both said bit lines and said source lines of non-selected ones of said memory transistors during read modes.
Claim 9
Independent Claim
49 words
A method of biasing an array of semiconductor memory transistors of a type having respective bit and source lines, comprising: establishing a predetermined bias voltage; and transmitting said bias voltage onto both said bit lines and said source lines of non-selected ones of said memory transistors during read modes.
Claim 10
Dependent Claim
64 words
A method according to claim 7, wherein said bias voltage is transmitted to said bit lines by a plurality of biasing transistors each having a source-to-drain path connected between said bias voltage and an associated bit line and a gate coupled to a supply voltage so that said bias voltage is more than the threshold voltage of said biasing transistors below the supply voltage.
Claim 11
Dependent Claim
83 words
A method according to claim 8, wherein said bias voltage is transmitted to said source lines by a plurality of associated corresponding source transistors each having a source-to-drain path connected between said bias line and an associated source line and each gate of which is coupled to the complement of a ground select decode signal voltage, VG, such that for non-selected transistors, the signal voltage VG is more than a threshold voltage of said source transistors greater than that on said bias line.
Claim 12
Dependent Claim
46 words
A method according to claim 9, wherein said bias voltage is established by coupling the source-to-drain path of a bias transistor between the supply voltage and said bias line and its gate to a reference voltage REF whose voltage is below that of the supply voltage.
Claim 13
Dependent Claim
62 words
A method according to claim 10, including establishing a bleed path for charge from said bias line to ground for draining charge from said bias line to ground through an impedance much larger than that through said bias transistor by connecting a conducting transistor between said bias line and ground whose channel size is much smaller than that of said bias transistor.
Claim 14
Dependent Claim
164 words
A biasing network for an array of non-volatile memory transistors coupled between associated bit and source lines, comprising: a bias line; a transistor having a source-to-drain path connected between the bias line and a supply voltage source V cc and a gate coupled to a reference voltage source REF whereby a voltage V bias is established on said bias line; a bit transistor having a source-to-drain path coupled between said bias line and a corresponding bit line and a gate coupled to a voltage source more than a threshold voltage of the bit transistor greater than V bias ; and a source transistor having a source-to-drain path coupled between said bias line and a corresponding source line and having a gate coupled to a decoded signal which is active when the corresponding memory transistor is not selected so that when said corresponding memory transistor is not selected during a read cycle, said source transistor transmits the voltage V bias to the corresponding source line.
Claim 15
Dependent Claim
164 words
A biasing network for an array of non-volatile memory transistors coupled between associated bit and source lines, comprising: a bias line; a transistor having a source-to-drain path connected between the bias line and a supply voltage source V cc and a gate coupled to a reference voltage source REF whereby a voltage V bias is established on said bias line; a bit transistor having a source-to-drain path coupled between said bias line and a corresponding bit line and a gate coupled to a voltage source more than a threshold voltage of the bit transistor greater than V bias ; and a source transistor having a source-to-drain path coupled between said bias line and a corresponding source line and having a gate coupled to a decoded signal which is active when the corresponding memory transistor is not selected so that when said corresponding memory transistor is not selected during a read cycle, said source transistor transmits the voltage V bias to the corresponding source line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |