US4729117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1986-03-19
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Granted: 1988-03-01
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Expires: 2006-03-19
Abstract
Abstract A semiconductor memory device is comprised of memory cells arranged in a matrix fashion; defective row line detect circuits for producing logic "1" when a defective row line is selectd to which a detective cell is connected; defective column line detect circuits for producing a logical "1" signal when a defective column line is selected to which a defective cell is connected; an AND gate for detecting the selection of defective cell using a logic value of the output signals from defective row and column line detect circuits; and an exclusive OR gate for exclusively ORing the read out data signal and the output signal from the AND gate to correct the defective data.
Inventors
- 👤 Yoshio Osaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:27
CPC Classifications
G; G11; G11C; G11C17/00; G11C29/00; G11C29/70; G11C29/88
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
241 words
A semiconductor memory device having a memory array with a plurality of memory cells arranged in a matrix of row and column lines wherein the memory cells are addressed by selecting row and column lines and where some of the memory cells may be defective; a row decoder for selecting a row line; a column decoder for selecting a column line, and a selected memory cell being connected between selected row and column lines; detect means for detecting a defective memory cell connected between selected row and column lines; and sense means for sensing the data of a detected defective memory cell; wherein said detect means comprises: row detect circuits connected to the output of said row decoder, said row detect circuits being programmed to detect a selected row line having a defective cell; column detect circuits connected to the output of said column decoder, said column detect circuits being programmed to detect a selected column line having a defective cell; means connected to said row and column detect circuits to receive the outputs thereof for detecting the selection of a defective memory cell based on the logic values of the outputs of said row and column detect circuits; and means connected to said sense means and said detect means to receive the outputs thereof and for inverting the logic value of the data sensed by said sense means based on the logic value of the output of said detect means.
Claim 2
Dependent Claim
241 words
A semiconductor memory device having a memory array with a plurality of memory cells arranged in a matrix of row and column lines wherein the memory cells are addressed by selecting row and column lines and where some of the memory cells may be defective; a row decoder for selecting a row line; a column decoder for selecting a column line, and a selected memory cell being connected between selected row and column lines; detect means for detecting a defective memory cell connected between selected row and column lines; and sense means for sensing the data of a detected defective memory cell; wherein said detect means comprises: row detect circuits connected to the output of said row decoder, said row detect circuits being programmed to detect a selected row line having a defective cell; column detect circuits connected to the output of said column decoder, said column detect circuits being programmed to detect a selected column line having a defective cell; means connected to said row and column detect circuits to receive the outputs thereof for detecting the selection of a defective memory cell based on the logic values of the outputs of said row and column detect circuits; and means connected to said sense means and said detect means to receive the outputs thereof and for inverting the logic value of the data sensed by said sense means based on the logic value of the output of said detect means.
Claim 3
Dependent Claim
166 words
A semiconductor memory device according to claim 1, wherein: said row decoder comprises a plurality of row decoders divided into a plurality of row decoder segments, said column decoder comprises a plurality of column decoders divided into a plurality of column decoder segments, and wherein said row detect circuits are divided into a plurality of row detect circuit segments corresponding to said row decoder segments, the outputs of said row detect circuits each constituting said row detect circuit segments and being interconnected; and said column detect circuits are divided into a plurality of segments corresponding to said column decoder segments, the outputs of said column detect circuits each constituting said column detect circuit segments and being interconnected; and said detect means comprises a plurality of selection detect sections, said selection detect sections selectively being connected to said row and column decoder segments for detecting the selection of the defective cells based on the logic levels of output signals of the selected row and column decoder segments.
References Cited (Backward Citations)
US4485471A
Cited
US4592024A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-01 | 1991-08-31 | 1992-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-01 | 1995-08-31 | 1996-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-01 | 1999-08-31 | 2000-03-01 | $7700.00 | Window Closed / Lapsed |