US4734885A
Expired / Lapsed
US
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Programming arrangement for programmable devices
Assignee: Intersil Corp
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Filing: 1985-10-17
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Granted: 1988-03-29
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Expires: 2005-10-17
Abstract
Abstract A programmable matrix has improved programming circuitry which allows the matrix to be programmed without raising the output terminals or power supply to higher than normal voltage levels. The circuitry includes a bidirectional output buffer and a multi-purpose input pin. The output buffer is provided with a control input and at least one buffer output. A switching device in the buffer provides a path to ground for programming current when a programming enable signal is applied to the control input and a concurrent operating level voltage pulse is applied to a selected buffer output. Programming current may be supplied via a dedicated input pin, but is preferably supplied via the multi-purpose input pin. A higher than normal operating voltage signal applied to the multi-purpose input pin acts to produce the programming enable signal which is subsequently applied to the buffer control input. This arrangement makes it unnecessary to elevate the voltage on the power supply input or the buffer outputs for programming purposes. The buffer outputs are isolated from programming currents and voltages by a second switching device in the bidirectional output buffer. The programming arrangement may be used with PROMs, PLAs and other programmable matrices.
Inventors
- 👤 Thomas M. Luich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:40
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
176 words
A programmable matrix having bit addressing inputs, bit outputs, a power supply input, a programming current input, and programming control circuitry, said control circuitry comprising: a multi-purpose input pin; programming current circuit means, connected to the programming current input, for providing a flow of programming current to the matrix; bidirectioeal output buffer means, connected to the bit outputs of the matrix and having at least one buffer output and having a control input for receiving a programming enable signal, for providing a current path for said programming current in response to application of a normal operating level voltage signal to said buffer output and substantially simultaneous application of a normal operating level voltage signal to the power supply input while said programming enable signal is present at the control input; and programming circuit means, connected to the multi-purpose input pin and to the control input of the bidirectional output buffer means, for producing said programming enaole signal in response to application of a first higher than normal operating level voltage signal to the multi-purpose input pin.
Claim 2
Dependent Claim
176 words
A programmable matrix having bit addressing inputs, bit outputs, a power supply input, a programming current input, and programming control circuitry, said control circuitry comprising: a multi-purpose input pin; programming current circuit means, connected to the programming current input, for providing a flow of programming current to the matrix; bidirectioeal output buffer means, connected to the bit outputs of the matrix and having at least one buffer output and having a control input for receiving a programming enable signal, for providing a current path for said programming current in response to application of a normal operating level voltage signal to said buffer output and substantially simultaneous application of a normal operating level voltage signal to the power supply input while said programming enable signal is present at the control input; and programming circuit means, connected to the multi-purpose input pin and to the control input of the bidirectional output buffer means, for producing said programming enaole signal in response to application of a first higher than normal operating level voltage signal to the multi-purpose input pin.
Claim 3
Dependent Claim
42 words
A programmable matrix according to claim 1, wherein said multi-purpose input pin is connected to operating circuit means for controlling an operating function of the matrix in response to application of a normal operating level voltage signal to the multi-purpose input pin.
Claim 4
Dependent Claim
56 words
A programmable matrix according to claim 1, wherein said control circuitry further comprises a programming current buffer means, having an input connected to the programming current circuit means, an output connected to said programming current input and a control input for receiving a programming enable signal, for controlling the flow of programming current to the matrix.
Claim 5
Dependent Claim
37 words
A programmable matrix according to claim 3, wherein said programming current buffer means input is connected to the multi-purpose input pin and, wherein said programming current circuit means is a higher than normal operating level voltage supply.
Claim 6
Dependent Claim
31 words
A programmable matrix according to claim 4, wherein said higher than normal operating level voltage supply is substantially higher in voltage than said first higher than normal operating level voltage signal.
Claim 7
Dependent Claim
28 words
A programmable matrix according to claim 1, wherein said control input of said bidirectional output buffer means is isolated from said buffer output by a first switching means.
Claim 8
Dependent Claim
69 words
A programmable matrix according to claim 6, wherein said first switching means is responsive to said normal operating level voltage signal applied to said buffer output and wherein said bidirectional output buffer means includes a second switching means for conducting a flow of programming current when said normal operating level voltage signal is applied to said buffer output and said programming enable signal is applied to said control input.
Claim 9
Dependent Claim
86 words
A programmable matrix according to claim 7, wherein said first switching means includes a first three terminal switch, having a first terminal connected to a reference potential, a second terminal connected to said control input, and a control terminal connected to said buffer output and, wherein said second switching means includes a second three terminal switch, having a first terminal connected to a reference potential, a second terminal connected to said bit outputs and a control terminal connected to said second terminal of said first switch.
Claim 10
Dependent Claim
73 words
A programmable matrix according to claim 1, wherein said bidirectional output buffer means includes a first transistor having a base connected to said buffer output, a collector connected to a reference potential, and an emitter connected by an impedance to said control input and by a diode to a base of a second transistor, said second transistor having an emitter connected to a reference potential and a collector connected to said bit outputs.
Claim 11
Dependent Claim
130 words
A programmable matrix having bit addressing inputs, bit outputs, a power supply input, a programming current input, and programming control circuitry, said control circuitry comprising: programming current circuit means, connected to the programming current input, for providing a flow of programming current to the matrix; circuit means for producing a programming enable signal; bidirectional buffer means, connected between said bit outputs and at least one buffer output and having an input mode and an output mode and a control input for receiving said programming enable signal to enable said input mode, for providing a current path for said programming current in response to selective application of a normal operating level voltage signal to said buffer output, and application of a normal operating level voltage signal to said power supply input.
Claim 12
Dependent Claim
130 words
A programmable matrix having bit addressing inputs, bit outputs, a power supply input, a programming current input, and programming control circuitry, said control circuitry comprising: programming current circuit means, connected to the programming current input, for providing a flow of programming current to the matrix; circuit means for producing a programming enable signal; bidirectional buffer means, connected between said bit outputs and at least one buffer output and having an input mode and an output mode and a control input for receiving said programming enable signal to enable said input mode, for providing a current path for said programming current in response to selective application of a normal operating level voltage signal to said buffer output, and application of a normal operating level voltage signal to said power supply input.
Claim 13
Dependent Claim
21 words
A programmable matrix according to claim 10, wherein said porgramming enable signal is a higher than normal operating level voltage signal.
Claim 14
Dependent Claim
29 words
A programmable matrix according to claim 11, wherein said control input pin of said bidirectional output buffer means is isolated from said buffer output by a first switching means.
Claim 15
Dependent Claim
69 words
A programmable matrix according to claim 12, wherein said first switching means is responsive to said normal operating level voltage signal applied to said buffer output and wherein said bidirectional output buffer means includes a second switching means for conducting a flow of programming current when said normal operating level voltage signal is applied to said buffer output and said programming enable signal is applied to said control input.
Claim 16
Dependent Claim
86 words
A programmable matrix according to claim 13, wherein said first switching means includes a first three terminal switch, having a first terminal connected to a reference potential, a second terminal connected to said control input, and a control terminal connected to said buffer output and, wherein said second switching means includes a second three terminal switch, having a first terminal connected to a reference potential, a second terminal connected to said bit outputs and a control terminal connected to said second terminal of said first switch.
Claim 17
Dependent Claim
73 words
A programmable matrix according to claim 10, wherein said bidirectional output buffer means includes a first transistor having a base connected to said buffer output, a collector connected to a reference potential, and an emitter connected by an impedance to said control input and by a diode to a base of a second transistor, said second transistor having an emitter connected to a reference potential and a collector connected to said bit outputs.
Claim 18
Independent Claim
131 words
A method of programming a matrix having bit addressing inputs, bit outputs, a power supply unit, a programming current input, a bidirectional output buffer connected to said bit outputs and having a buffer output and a control input, comprising the steps of: a. applying addressing level voltage signals to said bit addressing inputs to select a bit to be programmed; b. applying a programming level voltage signal to the programming current input; c. applying a normal operating level voltage signal to the power supply input; d. applying a programming enable signal to the control input of the bidirectional buffer; and e. selectively applying a normal logic level voltage signal to the buffer output to cause the bidirectional buffer to provide a path for programming current to flow from the selected bit.
Claim 19
Independent Claim
131 words
A method of programming a matrix having bit addressing inputs, bit outputs, a power supply unit, a programming current input, a bidirectional output buffer connected to said bit outputs and having a buffer output and a control input, comprising the steps of: a. applying addressing level voltage signals to said bit addressing inputs to select a bit to be programmed; b. applying a programming level voltage signal to the programming current input; c. applying a normal operating level voltage signal to the power supply input; d. applying a programming enable signal to the control input of the bidirectional buffer; and e. selectively applying a normal logic level voltage signal to the buffer output to cause the bidirectional buffer to provide a path for programming current to flow from the selected bit.
Claim 20
Dependent Claim
37 words
The method according to claim 16, wherein said programming enable signal is produced by applying a higher than normal logic level voltage signal to a multi-purpose input pin connected to the control input of the bi-directional buffer.
Claim 21
Dependent Claim
31 words
The method according to claim 17, wherein said programming level voltage signal is applied to said multi-purpose input pin and said multi-purpose input pin is connected to said programming current input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-29 | 1991-09-28 | 1992-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-29 | 1995-09-28 | 1996-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-29 | 1999-09-28 | 2000-03-29 | $7700.00 | Window Closed / Lapsed |