US4740484A
Expired / Lapsed
US
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Method in the manufacture of integrated circuits
Assignee: KTH Royal Institute of Technology
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Filing: 1986-03-04
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Granted: 1988-04-26
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Expires: 2006-03-04
Abstract
Abstract A method for manufacturing integrated circuits in which conductors and gate structures are built-up on a substrate plate, the conductors incorporating a layer of polycrystalline silicon and the gate structures including a gate electrode of polycrystalline silicon, where each of the gate structures is surrounded by doped source-and-drain-areas and where the gate electrode and the source-and-drain-areas respectively are metallized by depositing thereon a metal which reacts with the silicon from which the gate electrode and the source-and-drain-areas are comprised, so as to form a silicide layer. In accordance with the invention the gate electrode (3) is metallized in a first process stage. The source-and-drain-areas (18, 19) are metallized in a later process stage. Subsequent to metallizing the gate electrode in the first process stage, a protective layer (5) is applied to the metallized layer (4) of the gate electrode in a second process stage. All layers (16, 13, 7) present on the source-and-drain-areas (18, 19) are then removed to expose silicon, whereafter a metal (8) capable of reacting with the exposed silicon is deposited over the substrate, therewith to metallize (9, 10) the source-and-drain-areas (18, 19). In the second process stage, the protective layer (5) is given a thickness such that subsequent to the aforementioned etching process there remains a given, smallest thickness sufficient to ensure that the deposited metal (8) will not react with the silicon of the gate electrode (3, 4).
Inventors
- 👤 Hans Norstrom
- 👤 Sture Petersson
- 👤 Rudolf Buchta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/021; H10D64/60; H10D64/62; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10W20/064; H10W20/066
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
347 words
A method of manufacturing integrated circuits in which interconnects and gate structures are built upon a substrate plate, said interconnects incorporating a layer of polycrystalline silicon, said gate structures incorporating a gate electrode of polycrystalline silicon, said layers of polycrystalline silicon insulated from said substrate plate by a field oxide layer or a control oxide layer, where each of said gate structures is surrounded by doped source and drain areas and where said gate electrode and said source and drain areas are metallized by depositing thereon a metal which reacts with the silicon from which said gate electrode and source and drain areas are fabricated so as to form a silicide layer on said gate electrode and source and drain areas respectively, comprising: (a) metallizing said gate electrode with a first metallic layer; (b) applying a protective layer having a thickness onto said first metallic layer of said gate electrode; (c) applying an insulating layer over said gate structures, said source and drain areas and said interconnects; (d) removing all layers located on said source and drain areas and on areas beside said interconnects with a conventional suitable, direction-dependent dry etching method to etch away the insulating layer parallel with said substrate plate, such that the insulating layer is retained on vertical sides of said gate structure and on vertical sides of said interconnects in order to prevent short-circuiting between said gate electrode and associated source and drain areas or between two mutually adjacent interconnects such that silicon is exposed at said source and drain areas; (e) metallizing said source and drain areas separately from said gate electrode by depositing a second metallic layer over said substrate plate to react with said exposed silicon of said source and drain areas, said second metallic layer differing in composition from said first metallic layer; wherein said thickness of said protective layer is sufficient to ensure that said metal for metallizing said source and drain areas will not react with said silicon of said gate electrode, and said layer is of a composition which will not react with said metal.
Claim 2
Independent Claim
347 words
A method of manufacturing integrated circuits in which interconnects and gate structures are built upon a substrate plate, said interconnects incorporating a layer of polycrystalline silicon, said gate structures incorporating a gate electrode of polycrystalline silicon, said layers of polycrystalline silicon insulated from said substrate plate by a field oxide layer or a control oxide layer, where each of said gate structures is surrounded by doped source and drain areas and where said gate electrode and said source and drain areas are metallized by depositing thereon a metal which reacts with the silicon from which said gate electrode and source and drain areas are fabricated so as to form a silicide layer on said gate electrode and source and drain areas respectively, comprising: (a) metallizing said gate electrode with a first metallic layer; (b) applying a protective layer having a thickness onto said first metallic layer of said gate electrode; (c) applying an insulating layer over said gate structures, said source and drain areas and said interconnects; (d) removing all layers located on said source and drain areas and on areas beside said interconnects with a conventional suitable, direction-dependent dry etching method to etch away the insulating layer parallel with said substrate plate, such that the insulating layer is retained on vertical sides of said gate structure and on vertical sides of said interconnects in order to prevent short-circuiting between said gate electrode and associated source and drain areas or between two mutually adjacent interconnects such that silicon is exposed at said source and drain areas; (e) metallizing said source and drain areas separately from said gate electrode by depositing a second metallic layer over said substrate plate to react with said exposed silicon of said source and drain areas, said second metallic layer differing in composition from said first metallic layer; wherein said thickness of said protective layer is sufficient to ensure that said metal for metallizing said source and drain areas will not react with said silicon of said gate electrode, and said layer is of a composition which will not react with said metal.
Claim 3
Dependent Claim
31 words
The method according to claim 1, characterized in that said interconnects are also provided with said protective layer simultaneously with said gate structures, subsequent to metallizing the silicon of said interconnects.
Claim 4
Dependent Claim
21 words
The method according to claim 1 characterized in that said protective layer comprises a layer of silicon dioxide (SiO 2 ).
Claim 5
Dependent Claim
23 words
The method according to claim 1, characterized in that the protective layer comprises a layer of silicon nitride (SiO 3 N 4 ).
Claim 6
Dependent Claim
20 words
The method according to claim 1, characterized in that said insulating layer comprises silicon nitride (SiO 3 N 4 ).
Claim 7
Dependent Claim
18 words
The method according to claim 1, characterized in that said insulating layer comprises silicon dioxide (SiO 2 ).
Claim 8
Dependent Claim
42 words
The method according to claim 5 characterized by applying a silicon dioxide layer over the gate-structure, the source-and-drain-areas, and the interconnects subsequent to said second process in order to increase the adhesion of a silicon-nitride insulating-layer to the gate-structures and the conductors.
Claim 9
Dependent Claim
39 words
The method according to claim 1, characterized in that the second metal is deposited to metallize the source-and-drain-areas by applying tungsten hexafluoride (WF 6 ) in gas phase and under low pressure, tungsten (W) being precipitated onto the source-and-drain-areas.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |