US4740910A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor system
Assignee: Toshiba Corp
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Filing: 1986-06-26
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Granted: 1988-04-26
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Expires: 2006-06-26
Abstract
Abstract In this invention, when a service processor must request processing to all of n processors, it supplies a processing request to one of the n processors using a 1:1 inter-processor communication instruction. The processor receiving the request from the service processor then supplies a processing request to the remaining (n-1) processors using a 1:n inter-processor communication instruction. A bus control unit for controlling a system bus has a flag indicating whether or not the 1:1 (or 1:n) inter-processor communication instruction is sent. The service processor and other processors refer to the flag. When the flag is ON, issuance of the 1:1 (or 1:n) inter-processor communication instruction is inhibited to prevent contention between a plurality of requests.
Inventors
- 👤 Junihiko Sakata
- 👤 Takashi Hiraoka
- 👤 Ikuo Uchihori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:57
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F11/00; G06F11/22
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
A method for controlling a multiprocessor system having n processors (where n is a positive integer), a service processor, and a system bus comprising: (a) interconnecting said n processor and said service processor using a split bus control method; (b) controlling said system bus to exchange data thoughout said system; (c) issuing a 1:1 inter-processor communication instruction to selected ones of said n processors from said service processor; (d) issuing a 1:n inter-processor communication to the remaining processor from said processor which has received the 1:1 inter-processors communication instruction from said service processor; and (e) storing flag information having a first and second logic state in a bus control unit for controlling the execution of the 1:1 inter-processor communication instruction and the 1:n inter-processor communication instruction.
Claim 2
Independent Claim
126 words
A method for controlling a multiprocessor system having n processors (where n is a positive integer), a service processor, and a system bus comprising: (a) interconnecting said n processor and said service processor using a split bus control method; (b) controlling said system bus to exchange data thoughout said system; (c) issuing a 1:1 inter-processor communication instruction to selected ones of said n processors from said service processor; (d) issuing a 1:n inter-processor communication to the remaining processor from said processor which has received the 1:1 inter-processors communication instruction from said service processor; and (e) storing flag information having a first and second logic state in a bus control unit for controlling the execution of the 1:1 inter-processor communication instruction and the 1:n inter-processor communication instruction.
Claim 3
Dependent Claim
61 words
A method according to claim 1, wherein the step of issuing a 1:1 inter-processor communication includes executing a test and set instruction in said service processor for reading the stored flag information and setting the flag information to a second logic state at times when the flag information designates a first logic state prior to issuing the 1:1 inter-processor communication instruction.
Claim 4
Dependent Claim
39 words
A method according to claim 2, wherein said step of issuing a 1:1 inter-processor communication includes ceasing to issue the 1:1 inter-processor communication instruction at times when the flag information has already been set to the second logic state.
Claim 5
Dependent Claim
32 words
A method according to claim 1, wherein the steps of issuing a 1:n inter-processor communication to the remaining processors includes acknowledging that the received instruction has been issued from said service processor.
Claim 6
Dependent Claim
41 words
A method according to claim 1, wherein said step of issuing a 1:n inter-processor communication to the remaining processors includes a means for sending a response signal to said service processor when receiving a processing-request reception message from said remaining processors.
Claim 7
Dependent Claim
33 words
A method according to claim 5, wherein said step of sending a response signal to said service processor includes setting the flag information from the second logic state to the first logic state.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |