Memory cell having hot-hole injection erase mode

Claim 2

An integrated circuit memory, comprising: a semiconductor device for storing an electrical charge representing a data bit; and means for biasing said semiconductor device to operate said semiconductor device in a snap-back mode so that said data bit is erased from said semiconductor device.

Claim 3

An integrated circuit memory as set forth in claim 1, wherein said semiconductor device comprises: a transistor having a floating gate for storing said data bit; wherein said data bit is erased by hot-hole injection onto said floating gate during said snap-back mode.

Claim 4

A semiconductor integrated circuit memory component, comprising: a metal-oxide-semiconductor field effect transistor (MOSFET), havign a floating gate for storing an electrical charge representing a data bit; and mens for essentially nondestructively biasing said MOSFET to place said MOSFET into a snap-back mode such that hot-hole injection onto said floating gate neutralizes said electrical charge, whereby said data bit is erased.

Claim 5

A semiconductor integrated circuit memory component, comprising: a metal-oxide-semiconductor field effect transistor (MOSFET), havign a floating gate for storing an electrical charge representing a data bit; and mens for essentially nondestructively biasing said MOSFET to place said MOSFET into a snap-back mode such that hot-hole injection onto said floating gate neutralizes said electrical charge, whereby said data bit is erased.

Claim 6

In an electrically erasable programmable read only memory integrated circuit device, having means for producing a plurality of reference potentials, an improved memory cell comprising a substrate having a first conductivity type, a drain region in said substrate having a second conductivity type, a channel region between said source region and said drain region, a dielectric layer superposing said substrate, a first gate region in said dielectric layer superposing said channel region, for storing an electrical charge representing a bit of data, and a second gate region in said dielectric layer superposing and separated from said first gate region characterized in that means are provided for coupling said drain region, source region, and second gate region to said producing means and operating said cell so that said cell is biased into a snap-back condition to erase said data bit.

Claim 7

In an electrically erasable programmable read only memory integrated circuit device, having means for producing a plurality of reference potentials, an improved memory cell comprising a substrate having a first conductivity type, a drain region in said substrate having a second conductivity type, a channel region between said source region and said drain region, a dielectric layer superposing said substrate, a first gate region in said dielectric layer superposing said channel region, for storing an electrical charge representing a bit of data, and a second gate region in said dielectric layer superposing and separated from said first gate region characterized in that means are provided for coupling said drain region, source region, and second gate region to said producing means and operating said cell so that said cell is biased into a snap-back condition to erase said data bit.

Claim 8

The memory cell as set forth in claim 4 wherein said first gate region accepts hot-holes from said channel region during said snap-back condition, biasing said first gate region to neutralize said electrical charge and erase said data bit.

Claim 9

The cell as set forth in claim 5, wherein said drain region is coupled to receive a first electrical potential bias from said producing means.

Claim 10

The cell as set forth in claim 6, wherein said source region is coupled to an electrical ground potential for said device.

Claim 11

The cell as set forth in claim 7, wherein said second gate region is coupled to receive a second electrical potential bias from said producing means, whereby said first and second electrical potential biases cooperate to force said cell into said snap-back condition.

Claim 16

The method as set forth in claim 10, wherein said transistor is an n channel type, said step of biasing said source further comprises: coupling said source to a cell ground potential.

Claim 17

The method as set forth in claim 11, wherein said step of biasing said drain further comprises: coupling said source to a first positive potential for approximately 1 second.

Claim 18

The method as set forth in claim 12, wherein said step of pulsing further comprises: coupling siad control gate to a second positive potential of approximately twice the magnitude of said first positive potential for approximately 1 millisecond.

Claim 19

The method as set forth in claim 10, wherein said step of electrically biasing the drain comprises applying a bias voltage which is insufficient to create an avalanche breakdown.