In a video tape recorder having rotary recording, auxiliary and erasing heads, a circuit for short circuiting the auxiliary head during erasing

Claim 1

A helical scan tape recorder for recording signals in a plurality of skewed recording tracks on a record tape comprising: recording head means; auxiliary head means; erasing head means; tape guide means including a rotary body having the record tape wrapped on the periphery thereof, said rotary body carrying said recording head means, auxiliary head means and erasing head means; rotary transformer means for transmitting signals to said recording head means, auxiliary head means and erasing head means rotating with said rotary body and including a first section associated with said erasing head means and a second section having a primary winding connected to said auxiliary head means and a stationary secondary winding having its ends connected to output terminals; erase signal generating means including oscillating means, gate means connected between said oscillating means and said first rotary transformer section for applying an oscillating output of said oscillating means as said erase signal to said erasing head means when said gate means is enabled, and means for applying an erase timing control signal to said gate means for enabling the latter; and short circuit means responsive to said erase timing control signal for short circuiting said auxiliary head means whenever said gate means is enabled for applying said erase signal from said erase signal generating means to said erasing head means by way of said rotary transformer means, said short circuit means including an NPN-type transistor having an emitter-collector path connected between said output terminals for short circuiting the auxiliary head means when said NPN-type transistor is turned on, and means for turning on said NPN-type transistor including a PNP-type transistor having an emitter-collector path connected between a power source and a base electrode of said NPN-type transistor, and inverting means for applying an inverted version of said erase timing control signal to a base electrode of said PNP-type transistor, whereby said NPN-type transistor is turned on when said erase timing control signal is at a level for enabling said gate means.