US4745355A
Expired / Lapsed
US
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Weighted random pattern testing apparatus and method
Assignee: International Business Machines Corp
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Filing: 1987-05-11
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Granted: 1988-05-17
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Expires: 2007-05-11
Abstract
Abstract A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.
Inventors
- 👤 Edward B. Eichelberger
- 👤 Roger N. Langmaid
- 👤 Eric Lindbloom
- 👤 Franco Motika
- 👤 John L. Sinchak
- 👤 John A. Waicukauski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318566; G01R31/3183; G01R31/318385; G01R31/318544; G01R31/318547; G01R31/319; G01R31/31903; G01R31/31908; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G06F2201/00; G06F2201/83
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
Apparatus for testing a complex integrated circuit device having a very substantially greater number of internally interconnected logic elements than the number of input and output terminals of said device, thus rendering the internal elements inaccessible for discrete testing theoeof, comprising; (a) a plurality of pseudo-random pattern generators, one for each input terminal, each of said generators being operative to produce a uniquely different sequence of pseudo-random bit patterns, (b) means for applying the succession of bits from each of said generators to a different one of said input terminals in parallel as test input stimuli thereto. (c) signature register means operative responsive to all of the signals produced on said output terminals responsive to a succession of input stimuli to derive a signature which is a predetermined function of all of said output responses, and (d) and comparing means for comparing the thus-derived test signature with a signature of a known good device subjected to the same test stimuli.
Claim 2
Dependent Claim
160 words
Apparatus for testing a complex integrated circuit device having a very substantially greater number of internally interconnected logic elements than the number of input and output terminals of said device, thus rendering the internal elements inaccessible for discrete testing theoeof, comprising; (a) a plurality of pseudo-random pattern generators, one for each input terminal, each of said generators being operative to produce a uniquely different sequence of pseudo-random bit patterns, (b) means for applying the succession of bits from each of said generators to a different one of said input terminals in parallel as test input stimuli thereto. (c) signature register means operative responsive to all of the signals produced on said output terminals responsive to a succession of input stimuli to derive a signature which is a predetermined function of all of said output responses, and (d) and comparing means for comparing the thus-derived test signature with a signature of a known good device subjected to the same test stimuli.
Claim 3
Dependent Claim
55 words
The apparatus as defined in claim 1; further characterized in the provision of weighting means operative responsive to the bit pattern of each of said pattern generators for selectively altering the bit inputs to said input terminal to weight the normal distribution of ones and zeros inherent in a succession of pseudo-randomly ordered bit patterns.
Claim 4
Dependent Claim
67 words
The apparatus as defined in claim 1; wherein each of aid generators comprises a linear feedback shift register having the output of the last stage connected in parallel to each of a plurality of modulo two adders connected between predetermined successive stages of the shift register, each generator having a different combination of parallel connections, but all of which product the same number of patterns per cycle.
Claim 5
Dependent Claim
152 words
The apparatus as defined in claim 1 wherein said signature register means comprises; a plurality of first level signature registers each of which comprises a linear feedback shift register having the output of said last stage connected in parallel to each of a plurality of modulo-two adders connected between predetermined successive stages of the shift register, a plurality of further modulo-two adders connected between predetermined successive stages of the shift register each connected to a different one of said output terminals, and a second level signal register comprising a linear feedback shift register having the output of the last stage connected in parallel to each of a plurality of modulo-two adders connected between predetermined successive stages of the shift register, and a plurality of further modulo-two adders connected between predetermined stages of the shift register with each connected to the last stage of a different one of aid first level signature registers.
Claim 6
Dependent Claim
51 words
The apparatus as defined in claim 3; wherein the said generators each produce a succession of 2 n -1 different patterns, each consisting of n bits, in each cycle of operation, the succession being identically repeated in each cycle, whereby the bit configuration at every step within the cycle is predetermined.
Claim 7
Dependent Claim
47 words
The apparatus as defined in claim 4; wherein the signature register produces a signature which is a predetermined function of the succession of pseudo-random patterns and the test output responsives whereby the bit configuration of the test signature will manifest a good device or a bad device.
References Cited (Backward Citations)
US4503537A
Cited
US4594711A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |