Abstract In a computer device, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Additionally, it also is capable of implementing slightly more general operations than simply storing a zero or one value of a comparison. Basically, the instruction set in accordance with the invention compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set then conditionally nullifies the instruction following it, thus effecting a highly efficient execution of a sequence of instructions compared to the prior art.
A computer device comprising: an instruction further comprising: a. a first field for specifying a preselected condition in a comparison of two values; b. a second field for specifying one of said two values; c. a third field for specifying the other of said two values; d. a fourth field for specifying a register to be cleared unconditionally; and e. a fifth field for specifying the class of instruction; wherein said first, second, third, fourth, and fifth fields form a single instruction; means responsive to said instruction for accessing and clearing said register unconditionally; means for reading said two values specified by said second field and said third field; means for comparing said two values wherein said means for comparing is coupled to said means for reading; and means for nullifying a subsequent instruction without branching wherein said means for nullifying acts in response to said means for comparing.
Claim 2
Dependent Claim
149 words
A computer device comprising: an instruction further comprising: a. a first field for specifying a preselected condition in a comparison of two values; b. a second field for specifying one of said two values; c. a third field for specifying the other of said two values; d. a fourth field for specifying a register to be cleared unconditionally; and e. a fifth field for specifying the class of instruction; wherein said first, second, third, fourth, and fifth fields form a single instruction; means responsive to said instruction for accessing and clearing said register unconditionally; means for reading said two values specified by said second field and said third field; means for comparing said two values wherein said means for comparing is coupled to said means for reading; and means for nullifying a subsequent instruction without branching wherein said means for nullifying acts in response to said means for comparing.
Claim 3
Dependent Claim
32 words
The computer device as in claim 1, further comprising a means for operating, within one execution cycle, said means for accessing and clearing, said means for reading, and said means for comparing.