US4748628A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for correcting errors in digital audio signals
Assignee: Sony Corp
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Filing: 1986-10-22
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Granted: 1988-05-31
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Expires: 2006-10-22
Abstract
Abstract In correcting errors in a received digital data signal having information data a pair of parity series P and Q determined by the information data and a CRC code determined by the information data and the parity series; a parity check operation is performed for checking errors in either the parity series P or Q of the received digital data signal, error correcting operation is performed for correcting erroneous data of either the P series or the Q series data on the basis of an error pointer generated by the CRC code included in the received digital data signal, and a sequence of the parity check and error correcting operations is established for interposing at least one parity check operation among a series of error correcting operations.
Inventors
- 👤 Hisayoshi Moriwaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:20
CPC Classifications
H; H03; H03M; H03M13/00; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
163 words
An apparatus for correcting errors in a received digital data signal including information data, a first parity series based on said information data, a second parity series based on said information data and said first parity series, and a CRC code determined by said information data and said first and second parity series, comprising: parity check means for checking for errors in data of either said first parity series or said second parity series of said received digital data signal on the basis of error pointers generated by said CRC code included in the received digital data signal; error correcting means for correcting checked error in the data of either said first parity series or said second parity series data; and sequence control means coupled to said parity check means and said error correcting means for interposing at least one parity check operation by said parity check means in the midst of a plurality of error correcting operations by said error correcting means.
Claim 2
Independent Claim
163 words
An apparatus for correcting errors in a received digital data signal including information data, a first parity series based on said information data, a second parity series based on said information data and said first parity series, and a CRC code determined by said information data and said first and second parity series, comprising: parity check means for checking for errors in data of either said first parity series or said second parity series of said received digital data signal on the basis of error pointers generated by said CRC code included in the received digital data signal; error correcting means for correcting checked error in the data of either said first parity series or said second parity series data; and sequence control means coupled to said parity check means and said error correcting means for interposing at least one parity check operation by said parity check means in the midst of a plurality of error correcting operations by said error correcting means.
Claim 3
Dependent Claim
41 words
An apparatus according to claim 1; wherein said sequence control means causes a parity check operation by said parity check means at the beginning of each one of a number of series of error correcting operations by said error correcting means.
Claim 4
Dependent Claim
57 words
An apparatus according to claim 2; wherein said sequence control means includes counter means which counts the number of error pointers, and said at least one parity check operation interposed in the midst of error correcting operations is positioned among the latter on the basis of the number of said error pointers determined by said counter means.
Claim 5
Dependent Claim
81 words
An apparatus according to claim 1; wherein said sequence control means includes means providing a clock signal at the completion of each of said parity check and error correcting operations, counter means for counting said clock signal, a sequence switch means for selecting first and second parity check operations or error correcting operations in respect to said first and second parity series, and switch control means for controlling said sequence switch means in accordance with the value of said counter means.
Claim 6
Dependent Claim
112 words
An apparatus according to claim 1; wherein said sequence control means includes means providing a clock signal at the completion of each of said parity check and error correcting operations, counter means reset by said clock signal and being operative to count the error pointers in each interval between clock signals, switch means for selecting said first and second parity check and error correcting operations, means for comparing the count value of said counter means with a reference value and providing a compared output, and means for controlling said switch means to provide a sequence of said first and second parity check and error correcting operations in accordance with said compared output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |