US4751678A
Expired / Lapsed
US
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Erase circuit for CMOS EEPROM
Assignee: NXP USA Inc
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Filing: 1985-11-12
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Granted: 1988-06-14
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Expires: 2005-11-12
Abstract
Abstract An erase circuit for an EEPROM is provided which only uses enhancement type transistors. This eliminates having to use additional processing steps to provide depletion type transistors in a CMOS process. Enhancement type transistors are used to provide the erase voltage to the control gate of an electrically erasable memory cell. An additional enhancement type transistor is used to maintain the control gate in a non-floating condition during non-erase periods.
Inventors
- 👤 Kuppuswamy Raghunathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM characterized as having a read mode, a program mode, and an erase mode, the EEPROM further having an erase circuit comprising: a first enhancement transistor having a drain for receiving an erase signal, a gate for receiving a first control signal, and a source connected to an erase line; a second enhancement transistor having a drain coupled to the erase line, a gate for receiving a second control signal, and a source coupled to the control gate of at least one of the memory cells; and coupling means for coupling a reference voltage to the control gate of the memory cell coupled to the second enhancement transistor when the EEPROM is in one of the read mode and program mode and the first and second enhancement transistors are disabled.
Claim 2
Dependent Claim
149 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM characterized as having a read mode, a program mode, and an erase mode, the EEPROM further having an erase circuit comprising: a first enhancement transistor having a drain for receiving an erase signal, a gate for receiving a first control signal, and a source connected to an erase line; a second enhancement transistor having a drain coupled to the erase line, a gate for receiving a second control signal, and a source coupled to the control gate of at least one of the memory cells; and coupling means for coupling a reference voltage to the control gate of the memory cell coupled to the second enhancement transistor when the EEPROM is in one of the read mode and program mode and the first and second enhancement transistors are disabled.
Claim 3
Dependent Claim
95 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM further having an erase circuit comprising: a first enhancement transistor for controllably coupling a voltage for erasing to an erase line; a second enhancement transistor for controllably coupling the erase line to the control gate of at least one of the memory cells; and coupling means for controllably coupling a reference voltage to the control gate of each of the memory cells at times when the first and second enhancement type transistors are not enabled.
Claim 4
Dependent Claim
95 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM further having an erase circuit comprising: a first enhancement transistor for controllably coupling a voltage for erasing to an erase line; a second enhancement transistor for controllably coupling the erase line to the control gate of at least one of the memory cells; and coupling means for controllably coupling a reference voltage to the control gate of each of the memory cells at times when the first and second enhancement type transistors are not enabled.
Claim 5
Dependent Claim
41 words
The EEPROM of claim 2 wherein the plurality of memory cells are grouped in a byte configuration and further includes a plurality of second enhancement type transistors to selectively couple each group of byte configured memory cells to the erase line.
Claim 6
Dependent Claim
143 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM characterized as having a read mode, a program mode, and an erase mode, the EEPROM further having an erase circuit comprising: a first enhancement transistor having a drain for receiving an erase signal, a gate for receiving a first control signal, and a source connected to an erase line; a second enhancement transistor having a drain coupled to the erase line, a gate for receiving a second control signal, and a source coupled to the control gate of at least one of the memory cells; and a third transistor having a drain connected to the control gate of the memory cell coupled to the second enhancement transistor, a gate for receiving a third control signal, and a source for receiving the reference voltage.
Claim 7
Dependent Claim
143 words
An EEPROM having a plurality of electrically erasable memory cells, each such memory cell having a control gate, the EEPROM characterized as having a read mode, a program mode, and an erase mode, the EEPROM further having an erase circuit comprising: a first enhancement transistor having a drain for receiving an erase signal, a gate for receiving a first control signal, and a source connected to an erase line; a second enhancement transistor having a drain coupled to the erase line, a gate for receiving a second control signal, and a source coupled to the control gate of at least one of the memory cells; and a third transistor having a drain connected to the control gate of the memory cell coupled to the second enhancement transistor, a gate for receiving a third control signal, and a source for receiving the reference voltage.
Claim 8
Dependent Claim
29 words
The EEPROM of claim 4 further comprising a fourth transistor which couples the reference voltage to the source of the third transistor in response to the third control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |