Memory control circuit permitting microcomputer system to utilize static and dynamic rams

Claim 1

An enable signal processing circuit for application in a microcomputing system in which a microprocessor supplying control signal outputs including read RD, write WR, interrupt acknowledge INTA and address latch enable ALE signals interacts with a memory circuit having a specified address and coupled to the microprocessor to receive and send data whereby the memory circuit comprises one of static memory circuit and dynamic memory circuit, and a memory decoder circuit coupled to supply chip enable signals to the memory circuit, in response to an enable signal input, the enable signal processing circuit comprising; gating circuitry for providing a properly timed enable signal to the memory decoder circuit including: a first AND logic circuit with hysteresis characteristics at its inputs and coupled to receive read RD, write WR and interrupt acknowledge INTA signals from the microprocessor, a polarity inverting circuit with hysteresis characteristic at its inputs and coupled to receive an address latch enable signal ALE from the microprocessor, an RS flip-flop comprising first and second NAND gates cross coupled with each other and having a reset input coupled to an output of the first AND logic circuit and a set input coupled to an output of the polarity inverting circuit, a D-type flip-flop having its D input coupled to receive an output of the RS flip-flop, and a clock input and an output terminal to supply an enable signal, a second AND logic circuit coupled to receive inputs from the first AND logic circuit and the polarity inverting circuit and having its output coupled to the clock input of the D-type flip-flop, and the enable signal at the output terminal of the D-type flip-flop is coupled to the memory decoder circuit whereby a properly timed chip enable signal may be applied to the memory circuit.