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US4757216A Expired / Lapsed US ⏱️ 0.0 years remaining

Logic circuit for selective performance of logical functions

Assignee: NEC Corp
•
Filing: 1986-12-16
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Granted: 1988-07-12
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Expires: 2006-12-16
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Abstract

Abstract A logic circuit capable of selection of logical functions has an input terminal supplied with a binary signal; a first transistor with a base electrode connected to the input terminal, a collector supplied with a first voltage, and an emitter producing a first output signal; a first resistor whose one end is connected to the emitter of the first transistor and the other is supplied with a second voltage; a second transistor having a base electrode supplied with a reference voltage whose level lies between levels of the first and second voltages, an emitter connected to the emitter of the first transistor, and a collector for providing a second output signal; a second resistor whose one end is connected to the collector electrode of the second transistor and the other supplied with the first voltage. A first circuit has a first threshold value so set that the first output signal is judged to be a predetermined logical value in response to the first binary signal and to be a logical value corresponding to a logical value of the second binary signal in response to the second binary signal. A second circuit has a different threshold value so set that the second output signal is judged to be a predetermined logical value in response to the second binary signal and to be a logical value corresponding to a logical value of the first binary signal in response to the first binary signal.

Inventors

  • 👤 Toshio Tanahashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 327 words
A logic circuit comprising: an input terminal supplied with one of a first binary signal of a first voltage level and a second voltage level and a second binary signal of a third voltage level and a fourth voltage level different from said first voltage level and said second voltage level; a first transistor having a base electrode connected to sad input terminal, a collector electrode supplied with a first voltage, and an emitter electrode producing a first output signal; a first resistor whose one end is connected to the emitter electrode of said first transistor and the other end is supplied with a second voltage; a second transistor having a base electrode supplied with a reference voltage whose level is between levels of said first and second voltages, an emitter electrode connected to the emitter electrode of said first transistor, and a collector electrode producing a second output signal; a second resistor whose one end is connected to the collector electrode of said second transistor and the other end is supplied with said first voltage; a first circuit which is fed with said first output signal and whose first threshold value is so set that said first output signal is judged to be a predetermined constant logical value regardless of logical values of said first binary signal in response to said first binary signal and to be a logical value corresponding to a logical value of said second binary signal in response to said second binary signal; and a second circuit which is fed with said second output signal and whose second threshold value, different from said first threshold value, is so set that said second output signal is judged to be a predetermined constant logical value regardless of logical values of said second binary signal in response to said second binary signal and to be a logical value corresponding to a logical value of said first binary signal in response to said first binary signal.
Claim 2
Dependent Claim 327 words
A logic circuit comprising: an input terminal supplied with one of a first binary signal of a first voltage level and a second voltage level and a second binary signal of a third voltage level and a fourth voltage level different from said first voltage level and said second voltage level; a first transistor having a base electrode connected to sad input terminal, a collector electrode supplied with a first voltage, and an emitter electrode producing a first output signal; a first resistor whose one end is connected to the emitter electrode of said first transistor and the other end is supplied with a second voltage; a second transistor having a base electrode supplied with a reference voltage whose level is between levels of said first and second voltages, an emitter electrode connected to the emitter electrode of said first transistor, and a collector electrode producing a second output signal; a second resistor whose one end is connected to the collector electrode of said second transistor and the other end is supplied with said first voltage; a first circuit which is fed with said first output signal and whose first threshold value is so set that said first output signal is judged to be a predetermined constant logical value regardless of logical values of said first binary signal in response to said first binary signal and to be a logical value corresponding to a logical value of said second binary signal in response to said second binary signal; and a second circuit which is fed with said second output signal and whose second threshold value, different from said first threshold value, is so set that said second output signal is judged to be a predetermined constant logical value regardless of logical values of said second binary signal in response to said second binary signal and to be a logical value corresponding to a logical value of said first binary signal in response to said first binary signal.
Claim 3
Dependent Claim 29 words
The logic circuit as claimed in claim 1, which is provided within an integrated circuit having a plurality of terminals, one of which is connected to said input terminal.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-07-12 1992-01-11 1992-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-07-12 1996-01-11 1996-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-07-12 2000-01-11 2000-07-12 $7700.00 Window Closed / Lapsed

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