US4763177A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read only memory with improved channel length isolation and method of forming
Assignee: Texas Instruments Inc
•
Filing: 1987-05-20
•
Granted: 1988-08-09
•
Expires: 2007-05-20
Abstract
Abstract A non-volatile memory wherein the channel of the floating gate memory devices is recessed.
Inventors
- 👤 James L. Paterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
115 words
A non-volatile memory cell formed in a substrate having a semiconductor surface portion of a first conductivity type, comprising: a source region and a drain region, each comprising a second conductivity type diffusion at the surface of said substrate having thick oxide thereover; a channel region comprising a portion of said substrate underlying a recess therein between said source and drain regions; a thin gate insulator overlying said channel region; sidewall dielectric covering the sidewalls of said recess; a floating gate comprising a dielectrically isolated conductive layer overlying said channel region and extending onto said thick oxide over said source and drain regions; and a control gate overlying and capacitively coupled to said floating gate.
Claim 2
Dependent Claim
115 words
A non-volatile memory cell formed in a substrate having a semiconductor surface portion of a first conductivity type, comprising: a source region and a drain region, each comprising a second conductivity type diffusion at the surface of said substrate having thick oxide thereover; a channel region comprising a portion of said substrate underlying a recess therein between said source and drain regions; a thin gate insulator overlying said channel region; sidewall dielectric covering the sidewalls of said recess; a floating gate comprising a dielectrically isolated conductive layer overlying said channel region and extending onto said thick oxide over said source and drain regions; and a control gate overlying and capacitively coupled to said floating gate.
Claim 3
Dependent Claim
18 words
The cell of claim 1, wherein said source/drain regions comprise metal silicide layers near the respective surfaces thereof.
Claim 4
Dependent Claim
28 words
The cell of claim 1, wherein said source and drain regions have a greater thickness of crystalline material above the plane of said gate insulator than below it.
Claim 5
Dependent Claim
30 words
The cell of claim 1, wherein said source and drain regions have an effective junction depth (with respect to the surface of said channel region) of less than 5000 Angstroms.
Claim 6
Dependent Claim
22 words
The cell of claim 1, wherein said recess has a depth more than half the thickness of said source and drain regions.
Claim 7
Dependent Claim
22 words
The cell of claim 1, wherein said floating gate has a minimum thickness more than half the minimum width of said recess.
Claim 8
Dependent Claim
92 words
A semiconductor structure comprising: a pair of spaced apart regions of conductivity-type determining impurity disposed in a face of a semiconductor body, an isolation trench disposed between said regions of impurity and extending into said semiconductor body by less than the depth of said regions of impurity, a layer of insulator material formed over said regions of impurity and covering the walls of said trench, and a layer of conductive material filling said trench, and extending onto the layer of insulator material over said regions of impurity, to form a floating gate.
Claim 9
Dependent Claim
92 words
A semiconductor structure comprising: a pair of spaced apart regions of conductivity-type determining impurity disposed in a face of a semiconductor body, an isolation trench disposed between said regions of impurity and extending into said semiconductor body by less than the depth of said regions of impurity, a layer of insulator material formed over said regions of impurity and covering the walls of said trench, and a layer of conductive material filling said trench, and extending onto the layer of insulator material over said regions of impurity, to form a floating gate.
Claim 10
Dependent Claim
35 words
The semiconductor structure of claim 7 and further comprising: a second layer of insulating material formed over said conductive layer, and a second layer of conductive material formed over said second layer of insulating material.
Claim 11
Dependent Claim
20 words
The semiconductor structure of claim 7 wherein said regions of impurity comprise metal silicide layers near the respective surfaces thereof.
Claim 12
Dependent Claim
113 words
A semiconductor structure comprising: a pair of spaced apart regions of conductivity-type determining impurity disposed in a face of a semiconductor body, an isolation trench disposed between said regions of impurity and extending into said semiconductor body, a layer of insulator material formed over said regions of impurity and covering the walls of said trench, the thickness of said layer on the side walls of said trench being greater than the thickness of the thinnest portion of said layer on the bottom wall of said trench, and a layer of conductive material filling said trench, and extending onto the layer of insulator material over said regions of impurity, to form a floating gate.
Claim 13
Dependent Claim
113 words
A semiconductor structure comprising: a pair of spaced apart regions of conductivity-type determining impurity disposed in a face of a semiconductor body, an isolation trench disposed between said regions of impurity and extending into said semiconductor body, a layer of insulator material formed over said regions of impurity and covering the walls of said trench, the thickness of said layer on the side walls of said trench being greater than the thickness of the thinnest portion of said layer on the bottom wall of said trench, and a layer of conductive material filling said trench, and extending onto the layer of insulator material over said regions of impurity, to form a floating gate.
Claim 14
Dependent Claim
22 words
The semiconductor structure of claim 10 wherein at least one of said regions of impurity adjoins a side of said isolation trench.
Claim 15
Dependent Claim
35 words
The semiconductor structure of claim 10 and further comprising: a second layer of insulating material formed over said conductive layer, and a second layer of conductive material formed over said second layer of insulating material.
Claim 16
Dependent Claim
20 words
The semiconductor structure of claim 10 wherein said regions of impurity comprise metal silicide layers near the respective surfaces thereof.
References Cited (Backward Citations)
US3984822A
Cited
JPS5263074A
Cited
US4243997A
Cited
US4222062A
Cited
US4101344A
Cited
US4199772A
Cited
US4122544A
Cited
US4112509A
Cited
US4151021A
Cited
JPS53118981A
Cited
JPS53125778A
Cited
US4222063A
Cited
JPS56126973A
Cited
US4364074A
Cited
JPS58220464A
Cited
DE3323433A1
Cited
US4541001A
Cited
JPS5961188A
Cited
JPS5978576A
Cited
JPS59154071A
Cited
US4593454A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |