US4771250A
Expired / Lapsed
US
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Digital phase-lock loop having an estimator and predictor of error
Assignee: California Institute of Technology
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Filing: 1987-08-13
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Granted: 1988-09-13
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Expires: 2007-08-13
Abstract
Abstract A digital phase-lock loop (DPLL) which generates a signal with a phase that approximates the phase of a received signal with a linear estimator. The effect of a complication associated with non-zero transport delays related to DPLL mechanization is then compensated by a predictor. The estimator provides recursive estimates of phase, frequency, and higher order derivatives, while the predictor compensates for transport lag inherent in the loop.
Inventors
- 👤 Joseph I. Statman
- 👤 William J. Hurd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:04
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093; H03L7/099; H03L7/0991
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
119 words
A digital phase-lock loop comprising a linear estimator means for recursive estimates of phase, frequency, and higher order derivatives, a predictor means for compensating transport lag inherent in said loop, a phase detector means with gain for comparing an input signal Q(z) with the output Q(z) of said predictor with a delay inherent in said loop, and a means for adding the output of said predictor having said inherent delay z -N to the output φ(z) of said detector, said loop having a closed-loop transfer function of the form H(z)=C(z)D(z)z.sup.-N where C(z) is an estimator transfer function, D(z) is a predictor function and z -N is said transport lag in units of loop update time inherent in said loop.
Claim 2
Dependent Claim
119 words
A digital phase-lock loop comprising a linear estimator means for recursive estimates of phase, frequency, and higher order derivatives, a predictor means for compensating transport lag inherent in said loop, a phase detector means with gain for comparing an input signal Q(z) with the output Q(z) of said predictor with a delay inherent in said loop, and a means for adding the output of said predictor having said inherent delay z -N to the output φ(z) of said detector, said loop having a closed-loop transfer function of the form H(z)=C(z)D(z)z.sup.-N where C(z) is an estimator transfer function, D(z) is a predictor function and z -N is said transport lag in units of loop update time inherent in said loop.
Claim 3
Dependent Claim
49 words
A digital phase-lock loop as defined in claim 1 wherein said estimator means and said predictor means with inherent transport delay are comprised of a digital filter having a transfer function S(z) and a numerically controlled oscillator having a transfer function Q(z), where said transfer function S(z) satisfies: ##EQU14##
Claim 4
Dependent Claim
53 words
A digital phase-lock loop as defined in claim 2 wherein said numerically controlled oscillator, said digital filter and said adding means are implemented by a programmed digital computer, and a separate numerical controlled oscillator having a transfer function Q(z) is provided between the output of said digital filter and said phase detection means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |